Clock Generator with Jitter Injection for High-Speed Signal Testing
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Solution Overview
Problem
Conventional multi-phase clock generators lack the capability to introduce jitter, making them unsuitable for jitter tests in high-speed communication devices, as they produce evenly spaced phases without jitter and struggle to inject high-frequency jitter into high-frequency clocks.
Innovation Solution
A clock generator with a multi-phase clock generating section and a jitter injecting section, which includes delay elements, phase detectors, and variable delay circuits to control jitter injection, allowing for the generation of a single-phase clock with injected jitter, enabling effective jitter testing in high-speed communication devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional multi-phase clock generator uses DLL or PLL to align phases of low-frequency clocks evenly, then the clock signals have precise phase spacing, but the generated clock has no jitter and cannot be used for jitter testing
Solution Approach 1:
The clock generator is divided into two independent functional sections: a multi-phase clock generating section (using DLL/PLL for precise phase alignment) and a jitter injecting section (with variable delay circuits). This segmentation allows each section to perform its specialized function optimally while resolving the contradiction between precision and jitter capability.
Solution Approach 2:
The patent merges the conventional multi-phase clock generator with a jitter injection mechanism by combining the clock generating section and jitter injecting section into a single integrated system. The output of the first section feeds into the second, enabling both precise phase spacing and controlled jitter injection simultaneously.
2Speed
If a conventional clock generator produces high-frequency multi-phase clocks, then the clock frequency is suitable for high-speed communication, but it becomes difficult to inject high-frequency jitter into the clock
Solution Approach 1:
The jitter is injected into the low-frequency multi-phase clock signals before they are combined to generate the final high-frequency single-phase clock. This preliminary injection approach allows easier control and implementation of jitter at lower frequencies, avoiding the difficulties of injecting high-frequency jitter directly into high-frequency clocks.
Solution Approach 2:
The low-frequency multi-phase clock signals serve as an intermediary medium. Jitter is injected into these intermediate signals using variable delay circuits, and then these jittered intermediate signals are combined to produce the final high-frequency clock with injected jitter, bypassing the difficulty of direct high-frequency jitter injection.
3Adaptability or versatility
If a clock generator uses variable delay circuits to inject jitter into each clock signal, then jitter can be effectively injected, but the device complexity increases
Solution Approach 1:
The variable delay circuits in the jitter injecting section are designed to handle multiple clock signals simultaneously, providing a universal solution for jitter injection across all phases. This multi-functionality reduces the need for separate complex circuits for each phase, thereby managing overall device complexity while maintaining versatile jitter injection capability.
Data Source
AI summary
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.