Clock Generator Jitter Tuning With Constant Frequency
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Solution Overview
Problem
Existing clock generators in integrated circuits face challenges in reducing area and power consumption while maintaining strict jitter specifications, as they often require multiple generators for various frequencies, leading to increased power consumption and limited ability to adjust jitter characteristics.
Innovation Solution
A clock generator with a phase detector, voltage generator, voltage-to-current converter, and oscillation circuit that adjusts jitter characteristics and power consumption by varying resistance and capacitance values based on control information, allowing for dynamic frequency generation and optimized jitter for different digital blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock generators are provided in the integrated circuit to generate clock signals with various frequencies, then the frequency versatility is improved, but the area and power consumption increase
Solution Approach 1:
The patent implements a single clock generator that can generate multiple clock frequencies by dynamically adjusting the oscillation frequency of the voltage-controlled oscillator (VCO) based on division ratio information. This allows one clock generator to perform the function of multiple clock generators, reducing area and power consumption while maintaining frequency versatility
Solution Approach 2:
The patent uses dynamic frequency adjustment by changing the oscillation frequency of the VCO in response to division ratio information. The oscillation frequency is dynamically modified to compensate for frequency division effects, enabling a single generator to produce multiple output frequencies without requiring multiple fixed-frequency generators
2Adaptability or versatility
If multiple clock generators are provided in the integrated circuit to generate clock signals with various frequencies, then the frequency versatility is improved, but the area increases
Solution Approach 1:
The patent implements a single clock generator that can generate multiple clock frequencies by dynamically adjusting the oscillation frequency of the voltage-controlled oscillator (VCO) based on division ratio information. This allows one clock generator to perform the function of multiple clock generators, reducing area and power consumption while maintaining frequency versatility
Solution Approach 2:
The patent combines the functions of multiple clock generators into a single integrated circuit block. By merging the frequency generation and frequency division functions into one unit with dynamic frequency adjustment capability, the patent eliminates the need for separate clock generator circuits, thereby reducing the overall area occupied
3Area of stationary object
If a single clock generator is provided to reduce area and power consumption, then the area and power consumption are reduced, but the jitter specification becomes difficult to meet
Solution Approach 1:
The patent changes the oscillation frequency parameter of the VCO dynamically based on the required division ratio. By adjusting the center frequency of the band-pass filter and the oscillation frequency of the VCO in response to division ratio information, the system maintains optimal jitter characteristics across different output frequencies while using a single clock generator
4Area of stationary object
If a single clock generator is provided to reduce area and power consumption, then the area and power consumption are reduced, but the jitter control flexibility is limited
Solution Approach 1:
The patent uses dynamic frequency adjustment by changing the oscillation frequency of the VCO in response to division ratio information. The oscillation frequency is dynamically modified to compensate for frequency division effects, enabling a single generator to produce multiple output frequencies with appropriate jitter characteristics for each frequency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient generation of clock signals with varying frequencies and jitter characteristics, reducing power consumption and area requirements while maintaining strict jitter specifications, allowing for dynamic scaling and optimization for different digital block requirements.
Implementation Method 1
a voltage-to-current converter configured to convert the control voltage into an internal current having a level based on a resistance value
Implementation Method 2
an oscillation circuit configured to generate the output clock having a frequency based on the level of the internal current and a capacitance value
Data Source
AI summary
The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information.