Programmable Clock Generator for IC Latency Reduction
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Solution Overview
Problem
Conventional clock signal management in integrated circuits faces challenges such as latency and synchronization issues when adjusting PLL frequencies, particularly in systems with multiple PLLs, which hinders efficient power management and functional testing.
Innovation Solution
The implementation of a programmable clock generator that allows for independent and frequent frequency changes without modifying the PLL frequency, using pulse skipping and quadrature clock signals to provide generated clock signals with high frequency granularity, and employing multiple clock generators to manage different clock domains efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If PLL frequency is adjusted to achieve power management, then power savings are improved, but latency increases due to re-locking time of several hundred microseconds
Solution Approach 1:
The system segments clock frequency control into two independent parts: PLL provides coarse frequency adjustment while a divider circuit provides fine frequency adjustment. This allows power management operations to use the divider for quick frequency changes without triggering PLL re-locking, thereby reducing latency while maintaining power savings benefits.
Solution Approach 2:
A divider circuit is introduced as an intermediary between the PLL output and the system clock. This divider acts as a buffer that can quickly adjust frequency in response to power management events without requiring the PLL to re-lock, thus mediating between power management requirements and latency constraints.
2Adaptability or versatility
If multiple PLLs are used to provide clock signals for different subsystems, then adaptability is improved, but system latency increases due to the greatest re-locking latency among all PLLs
Solution Approach 1:
Each subsystem's clock path is segmented to include a local divider circuit that can independently adjust frequency without affecting other subsystems. This allows individual subsystems to respond to power management events independently, preventing the system latency from being determined by the slowest PLL re-locking time.
Solution Approach 2:
The system implements dynamic frequency adjustment capability at the subsystem level through divider circuits that can quickly modify clock frequencies in response to local power management events, making each subsystem's clock adaptable without being constrained by centralized PLL re-locking delays.
3Use of energy by moving object
If PLL frequency is adjusted for power management, then power savings are improved, but synchronization complexity increases due to need for sophisticated design solutions
Solution Approach 1:
Divider circuits serve as intermediaries that simplify synchronization by providing a straightforward mechanism for frequency adjustment that doesn't require complex phase alignment or re-locking procedures. This reduces synchronization design complexity while maintaining power management effectiveness.
Solution Approach 2:
The system changes the approach to frequency adjustment by using divider ratios instead of PLL frequency multiplication/division. This parameter change simplifies the synchronization problem because divider-based frequency adjustment is inherently more stable and easier to synchronize across multiple subsystems.
4Measurement precision
If conventional clock manipulation techniques are used for functional and speed test, then debug capability is improved, but debug time increases due to latency during frequency adjustments
Solution Approach 1:
The clock control path is segmented to allow test equipment to manipulate the divider circuit independently of the PLL, enabling precise clock frequency adjustments for functional and speed testing without incurring PLL re-locking latency. This improves debug accuracy while reducing debug time.
Solution Approach 2:
The divider circuit is configured in advance to allow rapid frequency switching for test purposes. By having the divider ready to adjust frequency without triggering PLL re-locking, the system enables preliminary testing actions to be performed quickly and accurately.
Data Source
AI summary
An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.