On-Chip Clock Generator With PVT-Compensated Current Source
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Solution Overview
Problem
On-die clock generators exhibit significant variations across different process, voltage, and temperature corners, making existing trim by die methods complex and time-consuming.
Innovation Solution
A low power on-chip clock generator that uses a process, voltage, and temperature (PVT) compensated current source to generate a stable clock, employing a proportional to absolute temperature (PTAT) circuit and current mirror circuitry to minimize variations, with the clock period determined by carefully selected design parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional on-die clock generators are used, then the clock frequency can be generated, but significant variations occur across different process, voltage, and temperature corners
Solution Approach 1:
The patent employs a PTAT current source that generates a current proportional to absolute temperature, and an anti-PTAT current source that generates a current inversely proportional to temperature. By summing these currents, the temperature-dependent variations are compensated, achieving stable clock frequency across temperature corners without requiring complex external trimming circuits
Solution Approach 2:
The patent implements automatic PVT compensation through feedback mechanisms where the PTAT and anti-PTAT current sources continuously monitor and adjust for process, voltage, and temperature variations. This self-correcting system maintains stable clock output across PVT corners without external intervention, eliminating the need for complex trim-by-die testing
2Reliability
If trim by die method is used to reduce clock variations, then clock stability improves, but the testing process becomes complex and time consuming
Solution Approach 1:
The clock generator circuit performs self-compensation for PVT variations through integrated PTAT and anti-PTAT current sources. The circuit automatically adjusts for process, voltage, and temperature effects without requiring external trimming equipment or manual calibration, thereby eliminating time-consuming trim-by-die testing while maintaining clock stability
Solution Approach 2:
The patent extracts the PVT compensation function from external testing equipment and integrates it directly into the on-die clock generator circuit. By embedding the compensation mechanism within the clock generator itself, the need for complex external trim-by-die testing is eliminated, reducing testing time while maintaining reliability
3Reliability
If trim by die method is used to reduce clock variations, then clock stability improves, but the testing complexity increases
Solution Approach 1:
The clock generator circuit performs self-compensation for PVT variations through integrated PTAT and anti-PTAT current sources. The circuit automatically adjusts for process, voltage, and temperature effects without requiring external trimming equipment or manual calibration, thereby eliminating complex trim-by-die testing while maintaining clock stability
Solution Approach 2:
The patent integrates multiple functions into a single on-die clock generator circuit: clock frequency generation, PVT monitoring, and automatic compensation. This multi-functional integration eliminates the need for separate external trimming equipment and complex testing procedures, reducing testing complexity while maintaining clock stability across PVT corners
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable clock that is independent of process, voltage, and temperature variations, enhancing reliability at higher clock frequencies and simplifying the testing process.
Implementation Method 1
employing a proportional to absolute temperature (PTAT) circuit and current mirror circuitry to minimize variations
Data Source
AI summary
According to some embodiments, a process, voltage, and temperature compensated clock generator is disclosed. The clock generator may be a charge-charge clock generator including a first load capacitive element and a second load capacitive element. A process, voltage, and temperature compensated current source is coupled to the charge-charge clock generator, and is used to charge the first load capacitive element and the second load capacitive element.