Integrated Clock Generator with Local Quadrature Error Correction
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Solution Overview
Problem
Existing clock signal generators in integrated circuit memory devices, such as DDR SDRAM, suffer from quadrature errors and high power consumption due to the transmission of high-frequency quadrature signals over long distances, which are not effectively addressed by current quadrature error correctors (QECs) that lack noise filtering and operate at limited frequency ranges.
Innovation Solution
A clock generator system utilizing a phase controller, oscillator, duty cycle converter, clock divider, and duty cycle calibrator to generate quadrature clock signals with controlled phases and duty cycles, reducing power consumption and correcting quadrature errors through a digital phase-locked loop and duty cycle comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency quadrature signals are transmitted through the clock distribution network to distant data pins, then the data pins can receive clock signals for data processing, but power consumption increases and quadrature errors deteriorate
Solution Approach 1:
The patent divides the clock distribution system into multiple segments: a first clock distribution network transmitting divided-frequency clock signals to clock generators, and second clock distribution networks transmitting full-frequency quadrature clock signals from clock generators to data pins. This segmentation allows low-power long-distance transmission followed by localized high-frequency generation, reducing overall power consumption while maintaining data transmission speed.
Solution Approach 2:
The patent implements local clock generation at each clock generator location, where quadrature clock signals are generated locally from divided-frequency inputs. This local quality approach ensures that high-frequency signals are only transmitted over short distances from the clock generator to the data pin, minimizing power consumption and signal deterioration while maintaining the required speed performance.
2Speed
If high-frequency quadrature signals are transmitted through the clock distribution network to distant data pins, then the data pins can receive clock signals for data processing, but quadrature errors of the signals are easily deteriorated
Solution Approach 1:
The patent segments the signal transmission path into a first network for divided-frequency clock signals and second networks for full-frequency quadrature signals. By generating quadrature signals locally at clock generators positioned near data pins, the system minimizes the distance over which high-frequency signals travel, thereby maintaining signal quality and reducing quadrature errors while still achieving the required transmission speed.
Solution Approach 2:
The patent introduces clock generators as intermediary devices between the main clock distribution network and data pins. These intermediaries receive divided-frequency clock signals, generate high-frequency quadrature signals locally, and provide them to data pins. This intermediary approach ensures high signal quality at the point of use while maintaining efficient overall system operation.
3Reliability
If quadrature error corrector is used to correct quadrature errors, then signal accuracy improves, but power consumption increases because it operates at the frequency of input signals
Solution Approach 1:
The patent applies preliminary frequency division to clock signals before they are used to generate quadrature signals. By dividing the clock frequency first and then generating quadrature signals from the divided signals, the system achieves quadrature error correction at lower frequencies, significantly reducing the power consumption of the quadrature error corrector while maintaining signal accuracy.
Solution Approach 2:
The patent changes the frequency parameter of clock signals before quadrature generation. Instead of generating quadrature signals directly from high-frequency input signals, the system divides the frequency first, generates quadrature signals at the lower divided frequency, and then uses these for data pin operations. This parameter change reduces power consumption while maintaining the required signal accuracy through subsequent local quadrature generation.
4Productivity
If additional 25% duty cycle converter is required to transmit data at quadrature rate, then data transmission capability is achieved, but device complexity increases
Solution Approach 1:
The patent merges the duty cycle conversion function into the clock generator itself. The clock generator integrates the capability to generate quadrature clock signals with 25% duty cycle directly, eliminating the need for separate duty cycle converter circuits. This integration maintains data transmission capability while reducing overall device complexity by combining multiple functions into a single unified component.
Solution Approach 2:
The clock generator is designed as a universal component that performs multiple functions: frequency division, quadrature signal generation, duty cycle conversion to 25%, and local clock distribution. By making the clock generator multi-functional, the patent eliminates the need for separate dedicated circuits for each function, thereby maintaining full data transmission capability while reducing device complexity.
Data Source
AI summary
A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.