Multi-Phase Clock Generator With Resistive Delay for Fine Phase Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generators struggle to produce clock signals with fine phase steps for accurate timing control in electronic systems, as they often rely on coarse phase interpolation methods that are inadequate for modern electronic applications.
Innovation Solution
A clock generator using a multi-phase controllable oscillator with cascaded resistive components and an inverter configuration, along with a common-mode voltage-based frequency-locked loop circuit, to generate clock signals with precise phase control and reduce frequency offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock generators use coarse phase interpolation methods, then device complexity is reduced, but phase control precision deteriorates
Solution Approach 1:
The oscillator is divided into multiple independent oscillator cores (first oscillator core, second oscillator core, etc.), each generating clock signals with specific phase relationships. This segmentation allows precise phase control through individual core configuration while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent implements dynamic phase control by configuring oscillator cores with adjustable parameters (such as variable delay elements or tunable frequency components). This allows the system to adaptively adjust phase relationships between clock signals generated by different oscillator cores, achieving fine phase steps while maintaining system stability.
2Manufacturing precision
If conventional clock generators lack frequency offset correction, then device complexity is reduced, but timing accuracy deteriorates
Solution Approach 1:
The patent implements a frequency-locked loop (FLL) circuit that continuously monitors the frequency of clock signals generated by the oscillator cores and provides feedback control. The FLL compares the actual frequency with the target frequency and adjusts control parameters to eliminate frequency offsets, thereby improving timing accuracy while adding controlled complexity through the feedback mechanism.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A clock generator (100) has a multi-phase controllable oscillator (104). The multi-phase controllable oscillator (104) includes oscillator core circuits (122[i]), and has phase nodes (P[i]) at which clock signals (CKOUT[i]) with different phases are generated, respectively. Each oscillator core circuit (122[i]) includes a resistive component (202) and an inverter (204). The resistive component (202) is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator (104), wherein clock signals (CKOUT[i]) generated at the first phase node and the second phase node have adjacent phases. The resistive components (202[i]) of the oscillator core circuits (122[i]) are cascaded in a ring configuration. The inverter (204) receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator (104), and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.