Non-Overlapping Clock Generator for ADC Sampling Alignment
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Solution Overview
Problem
Conventional clock generation devices for time-interleaved analog-to-digital converters suffer from sampling timing mismatch due to differences in signal path lengths and asymmetric circuit configurations, leading to reduced circuit performance.
Innovation Solution
A clock generation device comprising a first delay unit, a frequency divider, an angle delay unit, and calculating units that generate non-overlapping output clocks by dividing and delaying input clocks, ensuring precise control over stop-sampling edges without the need for additional delay paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional non-overlapping clock generator paths are used to generate clocks CK1 and CK2, then the clock generation function is achieved, but sampling timing mismatch occurs due to different signal path lengths and asymmetric circuit configuration
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing symmetric circuit paths that were previously asymmetric. The clock generation circuit is reconfigured so that both clock paths CK1 and CK2 have identical structural components and signal path lengths from the input clock CLKin, eliminating the timing mismatch caused by the original asymmetric configuration.
Solution Approach 2:
The patent segments the clock generation function into identical modular path units. Each clock output path (CK1 and CK2) is divided into separate but identical segments including delay elements, buffer elements, and control logic, ensuring that each segment contributes equally to the overall timing and eliminating path length differences.
2Measurement precision
If additional delay paths are added to compensate for timing mismatch, then sampling timing accuracy is improved, but device complexity and signal path length increase
Solution Approach 1:
The patent extracts the delay compensation function from separate additional delay paths and integrates it directly into the main clock generation paths. The delay elements are embedded within the normal clock signal flow rather than being added as external compensation paths, eliminating the need for longer signal paths while maintaining timing accuracy.
Solution Approach 2:
The patent merges the timing adjustment function with the primary clock generation function. The delay and buffer elements are combined with the clock signal paths themselves rather than being separate compensation mechanisms, so that timing control is achieved without extending the overall signal path length.
Data Source
AI summary
A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.