Clock Generator Simulated Signal for Master Clock Interruption
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Solution Overview
Problem
Existing signal processing apparatuses face challenges in providing a cost-effective and compact clock signaling solution when the master clock signal is shut down or interrupted, particularly in shrinking product sizes where adding a crystal is not feasible due to bulkiness and expense.
Innovation Solution
A signal processing apparatus incorporating a digital phase lock loop (DPLL) circuit that generates a simulated clock signal when the master clock is interrupted, allowing continuous operation by selectively coupling between the internal clock signal and the simulated clock signal, thereby eliminating the need for an external crystal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external crystal is added to provide clock signaling when master clock is interrupted, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the external crystal oscillator with the internal phase-locked loop circuit to form an integrated clock system. The crystal and PLL share common circuitry and control mechanisms, allowing the system to use either the external crystal or internal oscillator depending on operational mode, thereby providing reliable clock signaling without proportionally increasing component count.
Solution Approach 2:
The external crystal oscillator is designed to serve multiple functions: it provides clock signaling during normal operation when master clock is active, and automatically takes over when master clock is interrupted. The same crystal component thus serves both as a backup clock source and as part of the primary clocking system, eliminating the need for separate dedicated backup components.
2Reliability
If an external crystal is added to provide clock signaling when master clock is interrupted, then reliability is improved, but product size increases
Solution Approach 1:
The patent integrates the external crystal oscillator into the existing PLL circuit footprint, utilizing shared circuitry and common mounting structures. This merging approach allows the crystal to be housed within or adjacent to the PLL package, minimizing the additional volume required while ensuring reliable clock signaling during master clock interruptions.
3Reliability
If an external crystal is added to provide clock signaling when master clock is interrupted, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The external crystal oscillator is designed as a multi-functional component that serves both primary and backup clocking roles. By eliminating the need for separate dedicated backup crystal components and their associated mounting hardware, the overall bill of materials is reduced. The single crystal serves multiple purposes across different operational states, thereby lowering manufacturing costs while maintaining reliability.
4Device complexity
If internal clock generator is used when master clock is interrupted, then device complexity is reduced, but clock signal accuracy deteriorates
Solution Approach 1:
The patent implements a dynamic clock source selection mechanism where the system automatically switches between the external crystal oscillator and internal clock generator based on the master clock status. When master clock is interrupted, the system dynamically transitions to using the external crystal which provides higher accuracy. This dynamic adaptation allows the system to maintain optimal clock signal accuracy throughout different operational states without requiring permanent high-accuracy components in all paths.
Data Source
AI summary
A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.