Clock Generator Delay Gating for Accurate Edges and Skew Alignment
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Solution Overview
Problem
Conventional clock generator systems face issues with requiring high frequency clock signals due to frequency dividing operations and suffer from skew problems caused by misalignment of input signals and delay selecting signals, leading to errors in output signals.
Innovation Solution
A clock generator system comprising a control circuit, a delay module, and a clock gating unit that generates a target clock signal by delaying a reference clock signal based on a delay selecting signal, allowing for correct clock signal edges without frequency dividing and self-aligning the delay selecting signal to mitigate skew issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency division is used to generate divided clock signals, then the delay module can operate at lower frequencies, but the original clock signal must be very high frequency which increases system complexity
Solution Approach 1:
The patent extracts the frequency division function from the clock generator and implements it within the delay module itself. The delay module directly generates divided clock signals (e.g., CLK_DIV2, CLK_DIV4) by selecting appropriate delay amounts, eliminating the need for separate frequency division circuits and reducing overall system complexity.
Solution Approach 2:
The delay module is designed to perform multiple functions: it delays the input clock signal to generate divided clock signals, selects specific clock edges, and provides configurable delay amounts. This multi-functionality consolidates what would otherwise require separate frequency division circuits, simplifying the system architecture.
2Adaptability or versatility
If delay selecting signals are used to control delay units, then flexible delay control is achieved, but skew problems occur due to mismatched input signals and delay selecting signals
Solution Approach 1:
The patent applies preliminary action by delaying the delay selecting signals themselves before they are used to control the delay units. This pre-delay ensures that the selection signals are synchronized with the clock signal edges, preventing skew problems and ensuring accurate timing control while maintaining the flexibility of selectable delay amounts.
Solution Approach 2:
The system uses feedback mechanisms where the delay module monitors the timing relationship between the clock signal and delay selecting signals, and automatically adjusts the delay amount to maintain proper synchronization. This feedback ensures that the flexible delay control does not compromise signal alignment accuracy.
3Speed
If high frequency clock signals are used to achieve high frequency divided signals, then the divided clock signal frequency is improved, but the clock signal edges become inaccurate and skew increases
Solution Approach 1:
The delay module applies preliminary delay to the clock signal before division, ensuring that the divided clock signals are generated with accurate edges. By pre-configuring the delay amounts and selecting appropriate division ratios, the system maintains edge accuracy even when generating high frequency divided signals, preventing the skew and inaccuracy problems associated with direct high frequency division.
Data Source
AI summary
A clock generator for generating a target clock signal, comprising: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the control circuit, for delaying the reference clock signal according to the delay selecting signal to generate a delayed reference clock signal; and a clock gating unit, coupled to the delay module and the control circuit, for receiving the delayed reference clock signal and the clock enable signal, and for passing the delayed reference clock signal according to the clock enable signal, to generate the target clock signal.