Clock Generator Download Sequencing for Faster Stable Operation
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Solution Overview
Problem
Traditional reconfigurable integrated circuits face inefficiencies due to the distribution of nonvolatile memory 'bit' information across multiple locations on a semiconductor die, leading to an inefficient memory structure and prolonged power-up times for clock generators, where certain time-keeping elements take considerable time to reach a stable operation state.
Innovation Solution
A novel architecture that sequentially transfers configuration data from nonvolatile memory to volatile memory during power-up, allowing clock elements to initiate operation as soon as they receive their configuration data, with a predetermined sequence optimizing the download sequence to reduce overall time to stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration data is stored in distributed nonvolatile memory locations throughout the semiconductor die, then every bit location has local memory support, but the memory structure becomes inefficient and power-up time increases
Solution Approach 1:
The patent consolidates distributed nonvolatile memory locations into a single centralized nonvolatile memory array. This merging eliminates the inefficiency of having memory support circuits at every die location while maintaining configuration data availability. The centralized structure reduces overall power-up time by enabling sequential download of configuration data to volatile memory rather than requiring all distributed locations to be simultaneously initialized.
2Manufacturing precision
If all clock elements wait for complete configuration download before operation, then configuration accuracy is ensured, but time to stable operation increases
Solution Approach 1:
The patent implements a sequential download mechanism where configuration data is transferred from nonvolatile memory to volatile memory in a predetermined order. Elements that can operate sooner receive their configuration data earlier in the sequence, allowing them to initiate operation before the complete configuration download finishes. This preliminary action approach maintains configuration accuracy through controlled sequencing while reducing overall time to stable operation.
Solution Approach 2:
The configuration download process is segmented into multiple sequential stages, with different clock elements receiving configuration data at different times based on their operational readiness. This segmentation allows the system to divide the configuration task into manageable portions, enabling early-operating elements to proceed while later elements await their configuration data, thereby optimizing the overall time to stable operation.
3Loss of time
If configuration data is downloaded sequentially to volatile memory, then power-up time is reduced, but memory access complexity increases
Solution Approach 1:
The patent introduces a sequencer as an intermediary component that manages the sequential download of configuration data from nonvolatile memory to volatile memory. This sequencer handles the complexity of memory access control by automatically managing the download sequence, eliminating the need for complex control logic in higher-level systems. The sequencer acts as a mediator that simplifies the overall system architecture while enabling efficient sequential data transfer.
Data Source
AI summary
Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.