Clock Generator for OLEDs Using Switching Units
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Solution Overview
Problem
Conventional clock generators for high-speed serial link systems are limited by delay times and feedback loops, restricting clock signal frequency to below 1 GHz due to structural constraints and operational stability requirements.
Innovation Solution
A clock generator design that eliminates delay times and feedback loops by using four switching units and two inverters, with control signals having a 50% duty ratio and 90° phase difference, allowing for high-frequency clock signal generation without feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If feedback loops are used in conventional clock generators, then operational stability is maintained, but clock signal frequency is limited to below 1 GHz due to delay times and feedback requirements
Solution Approach 1:
The patent extracts and removes the feedback loop from the clock generator circuit, eliminating the delay time constraint that limits frequency to below 1 GHz. The switching units operate in open-loop configuration, allowing clock signals to be generated at frequencies up to 3.5 GHz without feedback requirements.
Solution Approach 2:
The patent implements preliminary action by pre-configuring four switching units with specific control signals that have 50% duty ratio and 90° phase difference. This preliminary configuration enables the circuit to generate high-frequency clock signals directly without requiring feedback for stability, as the switching units are预先 arranged to operate correctly from the start.
2Speed
If delay times are required for feedback operation, then operational stability is ensured, but clock signal generation speed is reduced
Solution Approach 1:
The patent extracts and eliminates the delay time element from the clock generator by removing the feedback loop mechanism. The switching units operate without requiring signal feedback, thereby eliminating the minimum delay time constraint and enabling high-speed clock signal generation at frequencies up to 3.5 GHz.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the switching units with control signals that have specific characteristics (50% duty ratio, 90° phase difference). This preliminary configuration allows the circuit to operate immediately at high frequencies without requiring delay time for feedback stabilization.
3Productivity
If feedback loops are implemented, then clock signal stability is maintained, but frequency multiplication capability is limited
Solution Approach 1:
The patent segments the clock generator into four independent switching units, each controlled by specific control signals with 50% duty ratio and 90° phase difference. This segmentation allows each unit to operate independently at high frequencies, achieving frequency multiplication capability up to 3.5 GHz while maintaining stability through the structured control signal configuration rather than feedback loops.
Data Source
AI summary
A clock generator, which can be included in an Organic Light Emitting Display (OLED), includes four switching units and two inverters. Each of the switching units includes two transistors. Transistors of two switching units that are connected to a high-level voltage line are PMOS transistors, and transistors of two switching units that are connected to a low-level voltage line are NMOS transistors. The switching units are sequentially turned on/off in response to four control signals so that the clock generator generates a clock signal. Each of the control signals has a duty ratio of 50%, and there is a phase difference of 90° between the control signals. The clock signal alternates between a low level and a high level every ¼ of a cycle of each of the control signals.