Injection-Locked Clock Generator for Fast Wide-Range Re-Locking
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Solution Overview
Problem
Conventional phase-locked loop (PLL) multipliers incur latency penalties due to long re-lock times after frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility and a narrow input frequency range, hindering efficient power conservation in frequency-agile systems.
Innovation Solution
A frequency-agile, fast-locking clock multiplier unit that compares a variable-frequency input clock with a self-generated reference clock to rapidly lock the output clock to a frequency multiple, using a wide-range oscillator with spectrally staggered component oscillators and tunable MILOs to achieve low-latency frequency transitions across a broad range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase-locked loop (PLL) multipliers are used, then a broad input frequency range is achieved, but long re-lock times incur latency penalties
Solution Approach 1:
The patent segments the frequency multiplication function into multiple parallel paths: a conventional PLL path for broad frequency coverage and an injection-locked oscillator path for fast locking. By dividing the system into these functional segments operating in parallel, the invention achieves both broad input frequency range and fast re-lock time, resolving the technical contradiction between adaptability and time loss.
2Loss of time
If injection-locked oscillators are used, then fast lock times are achieved, but a narrow input frequency range limits frequency agility
Solution Approach 1:
The patent merges the injection-locked oscillator (providing fast lock time) with a conventional PLL (providing broad frequency range) into a unified clock multiplier system. The merging allows the system to leverage the speed advantage of injection-locked oscillators while maintaining the frequency range capability of PLLs, thereby resolving the contradiction between lock time and input frequency range.
3Use of energy by moving object
If frequency transitions are made rapid, then power conservation is improved, but frequency stability may be compromised during transitions
Solution Approach 1:
The patent applies preliminary action by pre-configuring the injection-locked oscillator with the correct division ratio and frequency settings before the actual frequency transition is needed. This preliminary preparation allows the system to execute rapid frequency transitions with minimal latency while maintaining frequency stability, as the oscillator is already primed and ready to lock quickly without requiring lengthy stabilization periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables extremely fast-locking operations over a wide range of input frequencies, reducing latency and power consumption by quickly adjusting the output clock frequency in response to input frequency changes, thus supporting efficient power management in mobile devices.
Implementation Method 1
injection-locked oscillators exhibit fast lock times, but tend to have a narrow input frequency range
Data Source
AI summary
In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.