Clock Glitch Monitoring Circuit for Dual-Edge Fault Detection
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Solution Overview
Problem
Conventional EMFI sensors for detecting clock glitches are large, technology-dependent, power-hungry, and require trimming for correct operation, failing to efficiently monitor narrow glitches that can cause CPU misbehavior.
Innovation Solution
A compact clock signal monitoring unit utilizing cross-coupled flip flops, XOR gates, and a delay element to detect glitches without trimming, with low power consumption and robustness to PVT variations, capable of monitoring both rising and falling edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EMFI sensors are used to detect clock glitches, then glitch detection capability is provided, but device area increases, power consumption increases, and trimming is required
Solution Approach 1:
The patent combines multiple detection functions into a single compact circuit by cross-coupling flip-flops to simultaneously detect both rising and falling edge glitches. The shared delay element and XOR gate structure merges what would traditionally require separate sensing circuits, reducing overall area while maintaining comprehensive glitch detection capability.
Solution Approach 2:
The monitoring unit is designed to detect both rising edge and falling edge clock glitches using the same circuit structure. The cross-coupled flip-flops and shared delay element provide universal detection capability for different types of clock glitches without requiring separate specialized sensors, thereby reducing area and eliminating trimming requirements.
2Reliability
If conventional EMFI sensors are used to detect clock glitches, then glitch detection capability is provided, but power consumption increases
Solution Approach 1:
The patent merges multiple detection functions into a single compact circuit by cross-coupling flip-flops to simultaneously detect both rising and falling edge glitches. The shared delay element and XOR gate structure merges what would traditionally require separate sensing circuits, reducing overall area while maintaining comprehensive glitch detection capability.
Solution Approach 2:
The monitoring unit is designed to detect both rising edge and falling edge clock glitches using the same circuit structure. The cross-coupled flip-flops and shared delay element provide universal detection capability for different types of clock glitches without requiring separate specialized sensors, thereby reducing area and eliminating trimming requirements.
3Reliability
If conventional EMFI sensors are used to detect clock glitches, then glitch detection capability is provided, but trimming is required for correct operation
Solution Approach 1:
The patent employs a delay element with a fixed delay time that is specifically designed to correspond to the minimum clock period. This parameter selection allows the circuit to inherently distinguish between valid clock transitions and glitches without requiring post-fabrication trimming or calibration, simplifying manufacturing while maintaining reliable detection.
4Ease of manufacture
If a delay element with fixed delay time is used, then trimming is eliminated, but detection accuracy for narrow glitches must be maintained
Solution Approach 1:
The patent employs a delay element with a fixed delay time that is specifically designed to correspond to the minimum clock period. This parameter selection allows the circuit to inherently distinguish between valid clock transitions and glitches without requiring post-fabrication trimming or calibration, simplifying manufacturing while maintaining reliable detection.
Data Source
AI summary
The present disclosure relates to a clock signal monitoring unit comprising first, second and third flip-flops, first and second XOR gates and a delay element being functionally interconnected in a specific way. The proposed clock signal monitoring unit can detect both a rising edge glitch and a falling edge glitch. In this way there is provided an area saving device, which does not require any trimming efforts, which can save a lot of space and time. Furthermore, the clock signal monitoring unit can have low electric power consumption because it uses as few as four clocked flip-flops implemented via Register Transfer Logic having an already tuned delay element. This makes it useful for designs that use both edges of the clock for correct operation.