Clock Glitch Detection Circuit Using Phase Comparison Feedback
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Solution Overview
Problem
Secure chips and systems are vulnerable to clock glitch attacks, where a hacker applies a brief clock signal disruption, leading to operational errors and unauthorized access.
Innovation Solution
A clock glitch detection circuit comprising a detection circuit and a logic circuit that compares the clock input signal with its filtered output to determine phase alignment, generating a glitch detection signal to indicate whether a clock glitch occurs, thereby protecting the system from such attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock glitch detection circuit is implemented to detect clock glitches, then system security against clock glitch attacks is improved, but device complexity increases due to the additional detection circuit components
Solution Approach 1:
The detection circuit is divided into two functional segments: a first detection unit that generates a first detection signal based on the clock input signal, and a second detection unit that generates a second detection signal based on the clock output signal. These segmented detection units work together to identify clock glitches through signal phase comparison, resolving the contradiction by organizing complexity into manageable functional parts while maintaining security.
Solution Approach 2:
A filter circuit is introduced as an intermediary component between the clock input signal and the detection logic. This filter circuit generates the clock output signal by filtering the clock input signal, and the detection circuit then compares phases between the input signal and this intermediary output signal to detect glitches, thereby managing system complexity through structured signal processing.
2Measurement precision
If phase comparison detection is performed between clock input and output signals, then clock glitch detection accuracy is improved, but measurement precision requirements increase
Solution Approach 1:
The detection circuit uses feedback mechanisms where the clock output signal (which has been filtered from the input signal) is fed back into the detection logic for phase comparison with the original clock input signal. This feedback approach enables accurate glitch detection by comparing the expected signal pattern with the actual filtered output, improving detection accuracy while managing measurement complexity through systematic feedback processing.
Data Source
AI summary
A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.