Clock Glitch Suppressor Circuit With Programmable Delay Window
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Solution Overview
Problem
Integrated circuits face challenges in suppressing glitches in clock signals due to weak and slow transitions, exacerbated by shrinking transistor geometries and reduced operating voltages, leading to issues like double-triggering and transient noise, which conventional filtering methods like low-pass filtering and Schmitt triggers often fail to adequately address.
Innovation Solution
The implementation of a circuit that includes a latch to detect transitions in the input clock signal and ignore subsequent transitions for a programmable, pin-selectable, or self-adapting time delta, using a multiplexer to selectively pass changes in the input clock signal only after the elapsed delay, thereby preventing glitch propagation with minimal delay to the active clock edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional filtering methods (low-pass filtering and Schmitt triggers) are used to suppress clock signal glitches, then glitch suppression is achieved, but signal delay increases and reliability under certain circumstances deteriorates
Solution Approach 1:
The circuit performs preliminary action by detecting clock transitions and initiating a predetermined time period delay before allowing the signal to pass. The delay circuit generates a delayed version of the clock signal, and the AND gate logic ensures that transitions occurring during the predetermined time period are blocked before they can propagate further into the circuit, thus preventing glitches in advance
Solution Approach 2:
The patent introduces intermediary elements (delay circuit, AND gates, and logic circuitry) between the input clock signal and the output to mediate signal transmission. These intermediaries filter out unwanted transitions by comparing the original clock signal with its delayed version, allowing only valid transitions to pass through while blocking glitches
2Device complexity
If the delay circuit uses a fixed predetermined time period, then circuit simplicity is maintained, but adaptability to different clock frequencies deteriorates
Solution Approach 1:
The patent implements dynamics by making the delay circuit programmable or adjustable. The predetermined time period can be modified based on the clock frequency being used, allowing the circuit to adapt to different operating conditions. This dynamic adjustment capability enables the same circuit structure to work effectively across a range of frequencies without requiring complete redesign
Data Source
AI summary
Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.