Clock Input Buffer With NMOS Loads and Capacitive Biasing

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Solution Overview

Problem

Existing clock input buffers struggle to maintain proper operation at higher frequencies without increasing current consumption, leading to unintended output amplitude issues at high frequencies.

Innovation Solution

The proposed solution involves replacing the resistive loads in traditional clock input buffers with NMOS transistors and incorporating capacitive devices and bias voltage generators to optimize the differential amplifier configuration, allowing the clock input buffers to operate at higher frequencies without increasing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional clock input buffers use resistive loads, then they can operate at lower frequencies, but they cannot maintain proper operation at higher frequencies without increasing current consumption

Engineering Contradiction:

Improveoperating frequencyVSAvoidcurrent consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent changes the load type from resistive to capacitive and introduces bias voltage generation, fundamentally altering the operating parameters of the clock input buffer to enable high-frequency operation without proportionally increasing current consumption

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the traditional resistive load mechanism with a capacitive load mechanism and bias voltage generation system, substituting the electrical mechanism to achieve better frequency-performance characteristics

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If clock input buffers operate at higher frequencies, then processing speed improves, but output amplitude becomes unintended and operation becomes improper

Engineering Contradiction:

Improveoperating frequencyVSAvoidoutput amplitude stability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The bias voltage generator provides feedback control by monitoring and adjusting the operating conditions of the clock input buffer to maintain proper output amplitude at high frequencies

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces bias voltage generation and capacitive loading, changing key electrical parameters to maintain output amplitude stability while operating at higher frequencies

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250118356A1Apparatus including clock input buffer

Publication Date: 2025.04.10 MICRON TECHNOLOGY INC

AI summary

Embodiments of the disclosure provide an apparatus comprising: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to gate nodes of the load transistors; and first and second capacitive devices. Gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. The first input transistor and the first load transistor are coupled to a first output. The second input transistor and the second load transistor are coupled to a second output. The gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. The first and second capacitive devices are coupled to the first and second inputs and to the gate nodes of the first and second load transistors, respectively.