Clock Signal Phase Generation Using Intermediate Clocks and Latch Selection
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Solution Overview
Problem
Conventional clock generation devices require large circuits to generate and select multiple phase information, leading to increased size and complexity, especially in applications like CCD imaging systems and large-scale SoCs, where maintaining symmetry and adjusting signal skew is challenging, resulting in higher fabrication costs.
Innovation Solution
A clock signal generation device that uses an intermediate clock generator to produce multi-phase intermediate clock signals with a minimum phase difference, reducing the number of phases needed and employing phase selectors and a latch circuit to generate a desired phase clock signal with high resolution in a smaller circuit size, utilizing counters, shift registers, and logic operations to synchronize and select clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock generation devices generate all pieces of candidate phase information by combining phase interpolation circuits, then phase information can be obtained, but circuit size increases
Solution Approach 1:
The invention segments the phase selection process into two independent stages: first selecting from intermediate clock signals with larger phase differences, then selecting from original clock signals. This segmentation reduces the total number of phase signals that need to be generated and selected simultaneously, thereby reducing circuit size while maintaining high phase resolution
Solution Approach 2:
The invention introduces intermediate clock signals as a mediator between the original multi-phase clock signals and the final selected clock signal. These intermediate signals have phase differences larger than the minimum phase difference of original signals, serving as a bridge that reduces the complexity of direct phase selection
2Adaptability or versatility
If multiple phase selectors are used in CCD imaging systems to handle around 15 phases, then desired phase can be selected, but circuit size increases further
Solution Approach 1:
The invention divides the phase selection task into two separate selection processes: first selecting from a reduced set of intermediate clock signals, then selecting from original clock signals. This segmentation reduces the number of phase selectors needed from one large-scale selector handling 15 phases to two smaller selectors handling fewer phases each, thereby reducing overall circuit size
Solution Approach 2:
Intermediate clock signals serve as a mediator that reduces the complexity of phase selection in CCD imaging systems. By first selecting from intermediate signals with larger phase differences, the system reduces the burden on subsequent phase selectors, enabling versatile phase selection with smaller circuitry
3Reliability
If conventional clock generation devices are incorporated in various parts of large-scale SoCs for skew adjustment, then skew can be adjusted, but circuit size of entire chip increases exponentially
Solution Approach 1:
The invention segments the clock signal generation into two stages with two separate phase selectors, reducing the complexity of each individual clock generation unit. This allows multiple such units to be distributed across different parts of a large-scale SoC for skew adjustment without causing exponential growth in total circuit size
Solution Approach 2:
Intermediate clock signals act as a mediator that simplifies the clock generation function incorporated in various parts of large-scale SoCs. By using intermediate signals with larger phase differences, each distributed clock generation unit becomes less complex, enabling effective skew adjustment across the chip without exponential increase in overall circuit size
4Adaptability or versatility
If phase selectors receive more than several tens of phases, then comprehensive phase selection is possible, but maintaining symmetry of signal path delay becomes difficult
Solution Approach 1:
The invention segments the phase selection into two stages, with each stage handling a smaller number of phases. This segmentation makes it feasible to maintain symmetry of signal path delay in each stage, as the reduced number of phases allows for more symmetric circuit implementation, thereby improving manufacturing precision
Solution Approach 2:
Intermediate clock signals serve as a mediator that reduces the number of phases each phase selector must handle. This reduction enables more symmetric signal path implementation in each selection stage, making it easier to maintain delay symmetry and improve manufacturing precision despite the overall comprehensive phase selection capability
Data Source
AI summary
In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.