Duty Cycle Corrected Clock Interpolation for Fast Phase Adjustment
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Solution Overview
Problem
Existing methods for correcting duty cycle errors in clock signals are inefficient, requiring numerous iterative adjustments and taking hundreds of clock cycles to achieve accuracy, which can delay the operation of digital circuits.
Innovation Solution
A duty cycle corrected clock signal generator circuit that includes a clock generator, duty phase interpolator, and duty cycle adjuster, using phase splitter and interpolator circuits to quickly correct duty cycle errors by generating and interpolating clock signals approximately 180 degrees out of phase, allowing for fine duty cycle adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative adjustment of adjustable delay circuits is used to correct duty cycle error, then duty cycle accuracy is improved, but correction time increases significantly (taking several hundreds of clock cycles)
Solution Approach 1:
The patent pre-generates multiple delayed clock signals with different delay amounts before duty cycle correction is needed. These pre-generated signals are stored in a buffer and ready for immediate selection, eliminating the need for iterative adjustment during actual operation. This allows the system to quickly switch to a corrected duty cycle signal without spending hundreds of clock cycles on iterative tuning.
Solution Approach 2:
The patent implements a dynamic selection mechanism that can quickly switch between different delayed clock signals based on the detected duty cycle error. Instead of statically adjusting one delay circuit iteratively, the system dynamically selects from multiple pre-prepared signals, enabling rapid adaptation and correction within a single or few clock cycles.
2Reliability
If iterative duty cycle correction is performed, then signal reliability is improved, but circuit operation is delayed (circuits must wait hundreds of clock cycles before operating)
Solution Approach 1:
Multiple delayed clock signals are pre-generated and buffered before the circuit needs to operate. This preliminary preparation ensures that when the circuit starts operation, immediately reliable corrected signals are available, eliminating the hundreds of clock cycle delay that would otherwise be required for iterative correction.
Solution Approach 2:
The patent introduces a buffer as an intermediary component that stores pre-generated delayed clock signals. This buffer acts as a mediator between the signal generation and the consuming circuits, allowing circuits to immediately access pre-corrected signals without waiting for iterative adjustment, thus maintaining both reliability and operational speed.
3Manufacturing precision
If adjustable delay circuits are used for duty cycle correction, then duty cycle control precision is improved, but device complexity increases (requiring iterative adjustment mechanisms)
Solution Approach 1:
The patent divides the duty cycle correction function into multiple independent delayed clock signal generators, each producing a signal with a specific predetermined delay. Instead of using one complex adjustable delay circuit with iterative control, the system segments the function into multiple simple, fixed-delay circuits whose outputs can be selectively combined, reducing the complexity of individual components while maintaining overall precision.
Solution Approach 2:
A buffer serves as an intermediary that simplifies the complexity by providing a ready-made storage mechanism for multiple delayed signals. This intermediary component eliminates the need for complex iterative adjustment logic, as the selection can be made directly from pre-prepared signals stored in the buffer, thereby reducing control circuit complexity while preserving precision.
Data Source
AI summary
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.