Clock Distribution Inverter Chain for Low-Frequency Spur Reduction

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Solution Overview

Problem

Clock distribution chains in electronic devices experience low frequency spurs in high frequency clock signals due to unregulated power supply voltage modulation, which affects clock signal edges and introduces spurious tones.

Innovation Solution

Incorporating a current-starved inverter in parallel or series with logic inverters in the clock distribution chain to adjust the clock driver current and counteract low frequency modulation of the power supply voltage, maintaining constant clock edge delay regardless of power supply changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a switching regulator is used to provide power supply voltage, then power supply efficiency is improved, but low frequency spurs are introduced in clock signals

Engineering Contradiction:

Improvepower supply efficiencyVSAvoidlow frequency spurs

Core Design Contradiction:

Loss of energyVSObject-generated harmful factors

Solution Approach 1:

A current-starved inverter is introduced as an intermediary component between the switching regulator and the clock distribution chain. This inverter adjusts its current consumption to counteract the low frequency modulation of the power supply voltage, thereby canceling out the spurs without requiring changes to the switching regulator itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention converts the harmful low frequency modulation of the power supply voltage into a useful effect by using a current-starved inverter that deliberately varies its current consumption in response to the power supply modulation. This creates an opposing effect that cancels the spurs, turning the harmful voltage modulation into a beneficial current modulation that reduces spurs.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Ease of operation

If logic inverters are used to drive clock signals, then clock signal distribution is achieved, but clock edge delay varies with power supply voltage changes

Engineering Contradiction:

Improveclock signal distributionVSAvoidclock edge delay

Core Design Contradiction:

Ease of operationVSStability of the object's composition

Solution Approach 1:

The current-starved inverter implements a feedback mechanism where its current consumption is dynamically adjusted based on the power supply voltage conditions. This feedback loop compensates for voltage variations, maintaining stable clock edge delay despite changes in power supply voltage.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The invention changes the current consumption parameter of the inverter dynamically to compensate for power supply voltage variations. By adjusting the current parameter of the current-starved inverter, the system maintains constant clock edge delay despite external voltage fluctuations.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11711081B2Low frequency power supply spur reduction in clock signals

Publication Date: 2023.07.25 XILINX INC

AI summary

Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.