Clock Island Power-Up Using Auxiliary Clock and Reset Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated electronic devices face challenges in managing the clock during transitions between power saving modes, especially when the clock is used externally and specific requirements for correct generation and propagation need to be satisfied, which is not adequately addressed by prior techniques.
Innovation Solution
The method involves supplying an auxiliary clock of reduced frequency during power-on and using external asynchronous reset commands until a power-up condition is asserted, allowing for efficient power management by switching between different power modes, including off, standby, sleep, and active conditions, using three distinct circuit islands with specific control logic and switches to manage clock propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock generating circuit is switched off for power saving, then power consumption is reduced, but correct clock generation and propagation during transitions becomes problematic
Solution Approach 1:
The patent divides the device into distinct power domains (always-on domain and switchable domain) with separate clock management. The always-on domain maintains a reference clock while the switchable domain uses a derived clock that can be independently controlled, allowing the clock generating circuit to be switched off without affecting overall system reliability.
Solution Approach 2:
The patent implements preliminary clock configuration where clock division ratios are pre-stored in configuration memory before power-up. When the device boots, the clock generating circuit uses these pre-configured values to quickly establish the correct clock frequency without requiring external intervention or complex real-time configuration, ensuring reliable clock generation during transitions.
2Loss of energy
If distinct power domains are implemented for power saving, then static power dissipation is reduced, but clock management complexity increases
Solution Approach 1:
The patent introduces a clock management unit as an intermediary component that bridges the always-on clock domain and the switchable clock domain. This unit handles the complexity of clock synchronization, frequency derivation, and transition management, shielding the rest of the system from the complexity while enabling efficient power saving through independent domain control.
Data Source
AI summary
A method for power saving in an integrated circuit device may include defining an off-switchable analog circuit island including an internal clock generating circuit, and at power-on of the integrated circuit device, supplying to clocked digital circuits of the integrated circuit device an auxiliary clock from the external controller. The auxiliary clock has a frequency determined by the external controller and being lower than the root clock signal. The method includes supplying external reset commands to the integrated circuit device until an active functioning condition of the integrated circuit device is asserted, and interrupting the supply of the auxiliary clock and enabling supply of the root clock signal to the clocked digital circuits when the active functioning condition of the integrated circuit device is asserted.