On-Die Clock Jitter Analyzer Using Delay Line Edge Detection
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Solution Overview
Problem
Conventional methods for evaluating and debugging system-on-chip (SoC) designs face challenges in accurately measuring clock jitter, which can lead to performance issues and failure of communication between components, especially during initial bring-up and silicon debug, due to the complexity of monitoring clock waveforms and the need for external analyzers.
Innovation Solution
An apparatus and method for measuring jitter of a clock under test using a delay line with fixed-delay elements, a clock divider circuit, an adjustable delay circuit, clocked latches, an edge detector circuit, and a counter circuit to detect and count transitions within a sampling time window, providing a self-referenced, internal solution that does not require external equipment or additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external analyzers are used to measure clock jitter, then measurement accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a self-service principle by integrating the jitter measurement functionality directly into the SoC device. The measurement apparatus uses the device's own internal resources (logic elements, delay lines, counters) to measure its own clock jitter without requiring external analyzers. This eliminates the need for complex external measurement equipment while maintaining measurement accuracy through on-die implementation.
Solution Approach 2:
The measurement apparatus is designed with multi-functionality, using the same delay line and logic elements for both normal device operation and jitter measurement. The delay line serves dual purposes: as part of the functional logic during operation and as a measurement reference during jitter analysis. This universal approach reduces overall device complexity by avoiding dedicated separate measurement hardware.
2Measurement precision
If external analyzers are used to measure clock jitter, then measurement accuracy is improved, but manufacturing cost increases
Solution Approach 1:
By making the device self-measuring, the patent eliminates the need for expensive external jitter analyzers during testing and validation. The measurement functionality is built-in using standard logic elements that are already part of the manufacturing process, thereby reducing additional manufacturing costs while maintaining measurement precision.
Solution Approach 2:
The patent uses inexpensive, readily available logic elements and delay lines that are standard in modern SoC fabrication processes. These components are already manufactured as part of the device and can be easily programmed and configured without requiring specialized expensive hardware, thus reducing overall manufacturing costs.
3Ease of operation
If clock waveforms are monitored during initial bring-up, then debugging capability is improved, but device complexity increases
Solution Approach 1:
The device performs self-diagnosis by automatically measuring and reporting its own clock jitter characteristics during initial bring-up and operation. This self-service debugging capability provides comprehensive monitoring without requiring complex external test equipment or manual waveform analysis, thereby improving ease of operation while keeping the added complexity minimal and integrated.
Data Source
AI summary
Methods and systems for on-die measuring jitter of a clock under test are presented. In an aspect, an apparatus comprises a delay line having a plurality of delay elements, the outputs of which are sampled at the expected transition time of the clock under test. The sampled outputs are provided to an edge detector that indicates the presence of the clock transition at a specific time, and a latching circuit stores a record of all the edge locations seen during a sampling window. In some aspects, a counting circuit counts and stores how many times the transition occurs at each specific time during the sampling window. The counts stored by the counting circuit provide histogram data that can be analyzed to determine the jitter characteristics of the clock under test.