Clock Jitter Filter Using Half-Period Delay Feedback
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Solution Overview
Problem
Existing electronic systems face challenges in reducing clock jitter, which can lead to slower circuit operation and inefficiency, particularly in ring oscillators and clock signal chains.
Innovation Solution
A clock jitter filter is introduced, comprising first jitter reducing circuitry with a clock delay circuit that delays and inverts the clock signal by an odd integer multiple of half a period, and a connection that provides feedback from the output to the input, effectively reducing clock jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ring oscillators are used instead of LC oscillators, then cost is reduced and space is saved, but clock jitter increases
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the ring oscillator and the digital circuit. This delay circuit compensates for the clock jitter generated by the ring oscillator, allowing the use of compact ring oscillators while maintaining timing accuracy required by digital circuits.
Solution Approach 2:
The patent employs feedback mechanisms where the delayed clock signal is fed back to adjust and stabilize the timing of subsequent clock cycles. This feedback loop reduces the accumulation of jitter over multiple cycles, enabling reliable operation with compact oscillators.
2Reliability
If worst case scenario clock cycle length is used for circuit design, then all operations can be completed reliably, but the circuit operates slower than potential maximum speed
Solution Approach 1:
The delay circuit dynamically adjusts the clock signal parameters (timing and phase) based on actual jitter conditions rather than using fixed worst-case values. This allows the circuit to operate at higher speeds when jitter conditions permit, while still guaranteeing reliable operation when needed.
3Ease of operation
If clock signal chains with multiple buffers are used, then signal distribution is improved, but clock jitter accumulates
Solution Approach 1:
The delay circuit serves as an intermediary that processes the clock signal after it passes through the buffer chain, compensating for jitter accumulated during signal distribution. This allows extensive signal distribution without proportional jitter accumulation.
Data Source
AI summary
A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.