Clock Jitter Emulation for IC Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Emulators currently fail to detect errors caused by jitter in clock signals during clock domain crossings in integrated circuit designs, as they emulate perfect clocks without incorporating jitter, leading to undetected errors in the emulation of integrated circuits.
Innovation Solution
A system that includes a clock generator with a random jitter generator, accumulator, comparator, and minimum operator to emulate clock signals with jitter, allowing for the simulation of real-world clock variations and error detection during clock domain crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If perfect clocks are used in the emulation environment, then the emulation system operates with ideal timing, but errors caused by jitter in real-world clock signals cannot be detected
Solution Approach 1:
The patent modifies the clock signal parameters by introducing jitter to the ideal clock waveform. The clock generator adds random timing variations to the clock edges, changing the parameter of clock precision from perfect to realistic, enabling detection of timing-related errors while maintaining the fundamental clock function.
Solution Approach 2:
The patent creates a copy of the ideal clock signal and modifies this copy to include jitter characteristics. Rather than changing the original perfect clock, a jittered version is generated for use in the emulation environment, allowing comparison between ideal and real-world behavior.
2Adaptability or versatility
If jitter is incorporated into clock signals, then real-world clock variations are simulated, but the emulation complexity increases
Solution Approach 1:
The clock generation system is segmented into distinct functional blocks: a perfect clock source, a jitter generation unit, and a combination circuit. This segmentation allows the complex function of generating jittered clocks to be broken down into manageable, independently configurable components.
Solution Approach 2:
The patent introduces an intermediary jitter generation stage between the ideal clock source and the emulated circuit. This intermediary component adds the realistic timing variations without requiring complete redesign of the clock distribution system, simplifying the overall implementation.
Data Source
AI summary
An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.