System Clock Jitter Correction Using Feedforward Phase Error Estimation
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Solution Overview
Problem
Existing frequency multiplier systems face limitations in correcting phase noise due to the limited bandwidth of feedback loops and the need for frequent phase comparisons, which restricts the accuracy and stability of the output frequency, especially when the ratio of output frequency to reference frequency is large.
Innovation Solution
A method is introduced to estimate the instantaneous phase error of a frequency multiplier and apply digital phase error corrections in a feedforward manner, comparing the frequency multiplier output to a reference signal at multiple instances within a reference signal period, allowing for improved phase noise correction by sampling and digitizing the analog reference signal and applying corrections to the ADC output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If feedback loop bandwidth is increased to correct phase noise more frequently, then phase noise correction capability is improved, but system stability is compromised
Solution Approach 1:
The patent segments the phase noise correction function into two independent parts: (1) a feedback loop that maintains system stability with limited bandwidth, and (2) a feedforward correction path that provides frequent phase error corrections without stability constraints. The phase detector output is split, with one path going through the traditional feedback loop and another path providing direct feedforward correction to the DCO, allowing high-frequency correction without compromising loop stability.
Solution Approach 2:
The patent introduces a feedforward correction path as an intermediary mechanism that mediates between the stable but slow feedback loop and the need for frequent phase corrections. This intermediary path takes phase error detections and applies them directly to the DCO phase without waiting for the feedback loop to respond, effectively decoupling the correction frequency from the loop stability requirements.
2Measurement precision
If phase comparisons are performed more frequently to improve correction accuracy, then phase error correction precision is improved, but device complexity increases
Solution Approach 1:
The phase detector serves multiple functions simultaneously: it detects phase errors for both the traditional feedback loop and the feedforward correction path. The same phase detector hardware provides phase error information to two different correction mechanisms, eliminating the need for separate detection circuits and reducing overall device complexity despite the enhanced correction capability.
Solution Approach 2:
The system uses its own phase detector output to generate the feedforward correction signal, making the correction mechanism self-sufficient. The phase error detection is performed by the existing phase detector, and the correction is applied using the same system resources without requiring external correction devices or additional complex infrastructure.
3Adaptability or versatility
If output frequency is increased to meet high-frequency application requirements, then application versatility is improved, but phase noise becomes more dominant
Solution Approach 1:
The feedforward correction path performs preliminary phase error correction before the error can significantly degrade the signal quality. By detecting and correcting phase errors in real-time through the direct feedforward path, the system proactively prevents phase noise from accumulating and becoming dominant, allowing higher output frequencies to be used with maintained signal integrity.
Data Source
AI summary
A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.