Clock Jitter Measurement Circuit for High-Speed Semiconductor Clocks
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Solution Overview
Problem
High-speed clock signals generated by clock generating circuits, such as PLL circuits, often exceed the measurement capabilities of existing systems, making it difficult to accurately measure jitter, especially when affected by power supply noise and inter-signal interference.
Innovation Solution
Incorporating a jitter measurement circuit with a logic circuit and a delay element that converts time-axis analog jitter information into digital values, allowing for accurate measurement of clock jitter without division, and using programmable frequency dividers to adjust clock frequencies, thereby isolating the measurement from noise and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock generating circuit operates at high speed, then the productivity and performance of the semiconductor device is improved, but the measurement precision of jitter becomes insufficient because existing measurement systems cannot accurately measure high-frequency jitter
Solution Approach 1:
The patent introduces a jitter measurement circuit as an intermediary component that specifically measures jitter at the output of the clock generating circuit. This measurement circuit includes delay elements and logic circuits that can handle high-frequency signals, acting as a mediator between the high-speed clock generator and the measurement system to enable accurate jitter measurement without being limited by the bandwidth constraints of conventional measurement equipment.
2Ease of operation
If frequency division is used to measure jitter, then the measurement system can handle lower frequencies, but the measurement precision of actual jitter is lost because division reduces the measurable jitter magnitude
Solution Approach 1:
The patent extracts the jitter measurement function from the main clock signal path by using a separate jitter measurement circuit that directly samples the clock signal without frequency division. The measurement circuit includes a delay element that creates a time reference and logic circuits that detect timing deviations, allowing direct measurement of actual jitter values without the signal processing steps that would alter or reduce the measurable jitter magnitude.
3Measurement precision
If the jitter measurement circuit is added to the semiconductor device, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges the jitter measurement circuit with the existing clock generating circuit by integrating the measurement functionality into the same semiconductor device. The jitter measurement circuit shares the clock signal source and uses similar fabrication processes, combining multiple functions (clock generation and jitter measurement) into a single integrated device rather than using separate external measurement equipment, thereby reducing overall system complexity.
Data Source
AI summary
A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.