Clock Jitter Cancellation Using Supply-Voltage-Proportional Delay
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Solution Overview
Problem
Existing jitter mitigation techniques in electronic devices, such as memory devices, often increase power consumption and latency due to the use of voltage regulators to suppress supply noise, which exacerbates misalignment between clock signals, particularly in high-speed interfaces like DDR.
Innovation Solution
A jitter cancellation component is introduced into the signal path between clock signals, introducing delay directly proportional to the supply voltage to offset fluctuations caused by other circuitry, with a control algorithm adjusting the delay to minimize jitter, thereby maintaining synchronization without increasing power consumption or latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage regulators are used to suppress supply noise, then power supply stability is improved, but power consumption increases and latency increases
Solution Approach 1:
The patent extracts and removes the voltage regulator component from the system entirely. Instead of using traditional voltage regulation to suppress supply noise, the invention uses a delay circuit that introduces delay proportional to supply voltage fluctuations, thereby canceling jitter without requiring power-consuming voltage regulators.
Solution Approach 2:
The patent replaces the electrical/mechanical voltage regulation system with a timing-based delay circuit system. The delay circuit uses the relationship between supply voltage and circuit delay to convert voltage fluctuations into compensating timing adjustments, substituting active power-consuming regulation with passive timing-based compensation.
2Reliability
If voltage regulators are used to suppress supply noise, then power supply stability is improved, but latency increases
Solution Approach 1:
The patent removes the voltage regulator component that causes latency, replacing it with a delay circuit that introduces minimal timing adjustments. The delay circuit compensates for supply noise effects without the inherent latency penalty of traditional voltage regulation mechanisms.
Solution Approach 2:
The patent substitutes the latency-introducing voltage regulation mechanism with a timing-based delay circuit that operates in the time domain rather than the voltage domain, achieving supply noise suppression with minimal latency impact.
3Reliability
If delay circuit is introduced to offset supply voltage fluctuations, then jitter between clock signals is reduced, but device complexity increases
Solution Approach 1:
The delay circuit serves multiple functions simultaneously: it provides the intended delay function for clock signal timing while also acting as a jitter cancellation mechanism. By making the delay proportional to supply voltage, it automatically compensates for supply noise effects without requiring separate compensation circuits.
Solution Approach 2:
The patent changes the delay parameter of the circuit to be proportional to supply voltage fluctuations. This parameter change allows the same delay circuit to serve dual purposes: normal clock timing and automatic jitter cancellation based on supply voltage conditions.
Data Source
AI summary
Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.