Clock Lane Selection Unit for Interchangeable Signal Lanes
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Solution Overview
Problem
Current clock forward interfaces lack adaptability to interchange between clock and data lanes, making it difficult for receivers to effectively communicate with transmitters that interchange these signals.
Innovation Solution
An integrated circuit with a multi-lane interface and clock lane selection units that can dynamically select and sample signals from multiple lanes, allowing for interchangeable clock and data lanes, enabling the receiver to adapt to various signal configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the receiver uses a fixed clock lane configuration, then the circuit design is simple, but it cannot adapt to transmitters that interchange clock and data lanes
Solution Approach 1:
The patent implements dynamic lane assignment by allowing the receiver to identify and adapt to the actual clock lane configuration (either lane 0 or lane 1) used by the transmitter. The receiver dynamically adjusts its internal lane mapping based on detection of the transmitter's lane assignment, enabling flexibility without requiring hardware reconfiguration. This resolves the contradiction by making the system adaptable while maintaining relatively simple circuitry through software/firmware-based dynamic adjustment.
2Adaptability or versatility
If the receiver adds lane interchange capability, then adaptability improves, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by having the receiver detect and identify the transmitter's lane configuration during the initialization or training phase before actual data transmission begins. The receiver performs lane identification and configures its internal mapping in advance, so that when data transmission starts, the lane interchange capability is already established without adding complexity to the core transmission circuitry. This allows adaptability to be achieved while keeping the device complexity manageable.
3Reliability
If the receiver uses separate dedicated clock lane, then clock signal reception is reliable, but it cannot utilize data lanes for clock signals when needed
Solution Approach 1:
The patent implements universality by enabling the receiver to treat any lane (lane 0 or lane 1) as the clock lane depending on the transmitter's configuration. Instead of dedicating a specific lane for clock signals, the receiver is designed to universally accept clock signals from either lane through dynamic identification and adaptation. This allows the same physical lane to serve different functions (clock or data) based on configuration, achieving both reliability through proper clock signal reception and flexibility in lane utilization.
Data Source
AI summary
An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.