Clock Latch Fault Flag Circuit for Single Bit Upset Detection
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Solution Overview
Problem
Existing memory systems face challenges in detecting and addressing single bit upsets in clock latches, which can lead to data corruption and operational failures due to radiation-induced errors, especially in self-timed memory cells where internal clock generation is critical.
Innovation Solution
A failure determination circuit using a master and slave latch arrangement that generates a fault flag signal based on the internal and external clock signals, allowing for the detection of single bit upsets by latching the fault flag signal during specific clock cycles, indicating the presence of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock latch is used to generate internal clock signals in self-timed memory cells, then the memory operation speed is improved, but the system becomes vulnerable to radiation-induced single bit upsets that can cause data corruption
Solution Approach 1:
The patent applies preliminary action by proactively detecting potential single bit upsets in the clock latch before they can cause data corruption. The detection circuit monitors the clock latch output and generates an early warning signal when an upset is detected, allowing the system to take preventive measures before the error propagates to stored data.
Solution Approach 2:
The patent implements feedback by creating a closed-loop monitoring system where the output of the clock latch is continuously fed back to a detection circuit. This feedback mechanism allows real-time monitoring of the clock signal integrity and enables the system to detect and respond to radiation-induced upsets dynamically.
2Reliability
If radiation shielding is added to protect against single bit upsets, then reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces an intermediary detection circuit that acts as a mediator between the clock latch and the rest of the memory system. Rather than adding physical shielding that would increase device complexity, the intermediary circuit electronically monitors for upsets and generates detection signals, providing protection through software/logic层面的 intervention rather than physical barriers.
3Measurement precision
If the memory system continuously monitors for single bit upsets, then detection capability is improved, but energy consumption increases
Solution Approach 1:
The patent applies self-service by designing the detection circuit to utilize the existing clock latch structure and signals rather than requiring a completely separate monitoring system. The detection circuit leverages the self-timed nature of the memory cells and the existing clock generation mechanism, allowing the system to monitor itself without requiring additional external control signals or excessive energy input.
Data Source
AI summary
A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.