Clock Domain Latching Pulse for Skew-Tolerant Ratioed Clocks
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Solution Overview
Problem
In high-speed digital communication systems with multiple clock domains, phase jitter between clocks leads to poor timing margins and increased bit-error-rate due to varying phase relationships and clock skew, making it challenging to determine when clocks are aligned, especially when their frequencies are not integral multiples.
Innovation Solution
A data communications system that generates a pulse to indicate when data can be latched across clock domains, with the pulse occurring at a specific edge of one clock signal corresponding to the middle of the other clock signal's period, using a sync pulse generator and counter to detect selected cycles, allowing for deterministic and skew-tolerant data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is sampled at fixed clock edges without skew tolerance, then timing implementation is simple, but timing margins deteriorate and bit-error-rate increases due to phase jitter
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal sampling points in a lookup table before data transfer occurs. The alignment circuit queries this pre-computed table to determine when to sample data, eliminating the need for complex real-time phase alignment while maintaining robust timing margins despite clock skew and jitter.
2Reliability
If SRAM FIFO is used as brute force solution for clock domain crossing, then reliability improves, but area overhead and design complexity increase significantly
Solution Approach 1:
The patent extracts the essential function of clock domain crossing from complex SRAM FIFO structures and implements it using a minimal alignment circuit with lookup table. This removes the unnecessary complexity and large area overhead of traditional FIFO-based solutions while maintaining deterministic and reliable data transfer across clock domains with non-integral frequency ratios.
3Adaptability or versatility
If clock frequencies have non-integral ratios, then design flexibility improves, but determining clock alignment becomes difficult
Solution Approach 1:
The patent introduces an intermediary alignment circuit that uses a lookup table to mediate between clocks with non-integral frequency ratios. This intermediary structure pre-computes alignment points and provides deterministic sampling timing, making it easy to determine when to sample data even when clock frequency ratios are complex or non-integral.
Data Source
AI summary
A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.