Computing Device Clock Synchronization via Latency Compensation
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Solution Overview
Problem
Internal computing device clocks in power systems are prone to errors and inaccuracies due to 'drift' over time and power fluctuations, making them unreliable for providing accurate time-stamping of events in power system monitoring and fault detection.
Innovation Solution
A system and method that synchronizes the computing device clock with a master clock using latency adjustments derived from total system latency calculations, ensuring accurate time generation by coupling the computing device with a master clock device via a communications link and using loop-back commands and zero-crossing synchronized commands to determine and apply latency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal computing device clocks are used for time-stamping events, then the system operates autonomously without external dependencies, but the time accuracy deteriorates due to clock drift and power fluctuations
Solution Approach 1:
The patent introduces a master clock device as an intermediary between the computing device and the accurate time source. The master clock receives time data signals and processes them through latency compensation algorithms, acting as a mediator that eliminates the need for the computing device to directly implement complex synchronization protocols while ensuring accurate time-stamping
Solution Approach 2:
The system performs preliminary latency measurements by sending loop-back commands before actual time-stamping operations. The master clock device pre-calculates latency compensation values based on measured delays in the communication path, so that when events need time-stamping, the compensation is already in place and can be applied immediately without real-time calculation delays
2Measurement precision
If latency compensation is implemented to improve time accuracy, then event time-stamping precision is improved, but the device complexity increases due to additional synchronization components
Solution Approach 1:
The master clock device performs self-calibration by automatically measuring its own latency characteristics through loop-back commands. The system sends time data signals through the communication path and measures the round-trip delay, then automatically calculates and applies the appropriate compensation without requiring external calibration equipment or manual intervention
Solution Approach 2:
The patent combines multiple functions into the master clock device: it serves as the time source receiver, latency measurement instrument, compensation calculation engine, and time-stamping authority all in one device. This consolidation reduces overall system complexity compared to having separate components for each function while maintaining high time-stamping precision
Data Source
AI summary
A system and method provides accurate time generation in a computing device that includes a computing device clock and a microprocessor. The method includes determining a total system latency based on a delay incurred between issuance of a first command by the microprocessor and receipt of a first time-data signal by the microprocessor. The first time-data signal is representative of a master clock output of a master clock device at a first time. The method also includes deriving an accurate time from a second time-data signal. The second time-data signal is representative of the master clock output at a second time known by the microprocessor. The method further includes adjusting the accurate time based on a percentage of the total system latency to form a latency adjusted time, and applying the latency adjusted time to the computing device clock to synchronize the computing device clock to the master clock output.