Clock Level Conversion with Feedback Duty Ratio Correction
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Solution Overview
Problem
Existing level conversion circuits for clock signals, particularly in high-speed semiconductor integrated circuits, face challenges in maintaining a 50% duty ratio due to process variations and noise, especially in long clock lines, leading to performance degradation and inability to correct duty ratio when normal mode offset occurs.
Innovation Solution
A level conversion circuit with a duty correcting section that includes an integrating circuit, constant current source, and capacitive elements to measure and adjust the duty ratio, using a feedback loop to generate a correction signal that balances charging and discharging times, ensuring the output signal has a 50% duty ratio, even in the presence of common mode and normal mode variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level conversion circuit is used to convert CML clock signals to CMOS logic level signals, then level conversion is achieved, but duty ratio degradation occurs due to process variations and characteristics
Solution Approach 1:
The patent implements a duty correction circuit that measures the actual duty ratio of the converted clock signal and feeds back correction information to adjust the conversion timing. This closed-loop feedback mechanism compensates for process variations and characteristics, maintaining accurate 50% duty ratio despite manufacturing tolerances and environmental changes.
Solution Approach 2:
The invention dynamically adjusts conversion parameters (timing, threshold levels) based on measured duty ratio deviations. By changing these parameters in real-time according to actual signal characteristics, the circuit adapts to process variations and maintains precise duty ratio control throughout operation.
2Manufacturing precision
If cross-point correction is applied to correct duty ratio at the output, then duty ratio is improved at the output nodes, but normal mode offset cannot be corrected
Solution Approach 1:
The patent introduces an intermediary measurement and correction stage between the level conversion and final output. The duty correction circuit acts as a mediator that independently measures the converted signal's duty ratio and applies corrections without being constrained by the binary cross-point correction approach, enabling correction of normal mode offsets that previous methods could not address.
Solution Approach 2:
The correction function is segmented into independent measurement and adjustment stages. Rather than relying on a single cross-point correction mechanism, the patent divides the correction process into separate functional blocks that can independently address different error sources including normal mode offsets, providing more versatile correction capability.
3Speed
If complex level conversion circuits are used to handle high-speed signals, then signal transmission capability is improved, but circuit complexity increases and duty degradation becomes more pronounced
Solution Approach 1:
The patent employs feedback-based duty correction that automatically compensates for degradation without requiring complex pre-correction circuitry. This feedback approach maintains simplicity while achieving accurate duty ratio control at high speeds, avoiding the need for overly complex conversion circuits that would exacerbate duty degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively corrects the duty ratio of output signals to 50% without increasing delay time, addressing duty degradation in both common and normal modes, thereby improving the performance of synchronous circuits.
Implementation Method 1
a capacitive element connected to the current mirror circuit section and configured to carry out charging and discharging operations by using the corresponding current based on the output signal
Implementation Method 2
a current mirror circuit section configured to supply a current corresponding to a current supplied from the constant current source
Data Source
AI summary
A level conversion circuit includes an input section configured to receive a first signal of a first signal level and a correction signal and generates a second signal of a second signal level from the first signal and the correction signal. A level converting section converts the second signal into an output signal of a third signal level, and a duty correcting section generates the correction signal corresponding to a duty ratio of the output signal and outputs the correction signal to the input section.