Display Panel Through-Hole Structure for Balanced Clock Line Capacitance
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Solution Overview
Problem
The existing OLED display devices face issues with grooves above clock lines being offset, leading to excessive changes in parasitic capacitances that affect signal delay and display performance due to mask alignment deviations during the trenching process.
Innovation Solution
The display panel design includes a low-potential signal line with through holes arranged in an array, ensuring equal overlapping areas with clock signal lines, maintaining consistent parasitic capacitances by aligning the through holes symmetrically with clock signal lines to prevent signal delay differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If grooves are dug in the metal of the anode layer above clock signal lines to release water vapor, then water vapor release is improved, but mask alignment deviation causes groove offset relative to clock lines, leading to excessive parasitic capacitance changes and signal delay
Solution Approach 1:
The patent applies local quality by creating through-holes only in specific regions of the low-potential signal line that correspond to clock signal line positions. The through-holes are strategically placed to provide water vapor release paths precisely where needed (above clock lines) while avoiding unnecessary modifications in other areas, thus maintaining manufacturing precision while achieving the water vapor release function.
2Reliability
If through holes are arranged to ensure equal overlapping areas with clock signal lines, then parasitic capacitance consistency is improved, but the design complexity increases
Solution Approach 1:
The patent employs asymmetry in the through-hole design where the number of through-holes, their positions, and dimensions are deliberately made asymmetric relative to the low-potential signal line center. This asymmetric arrangement allows precise control of overlapping areas with clock signal lines to achieve consistent parasitic capacitances, while the asymmetry itself becomes a simplified design rule that reduces overall complexity compared to symmetric alternatives.
Solution Approach 2:
The patent applies parameter changes by adjusting the number, position, and dimensions of through-holes to optimize the overlapping area with clock signal lines. By varying these parameters, the design achieves consistent parasitic capacitances across different clock lines while maintaining a relatively simple overall structure.
Data Source
Figure 1(a)~1(c)
Figure 2(a)~2(f)
Figure 3(a)~4
AI summary
The present application provides display panels and display devices. In the display panel, the through holes are designed, so that when the position of the through holes is offset, an overlapping area of any clock signal line and the through holes remains unchanged, and the overlapping area of each clock signal line and the through holes is the same, so that the parasitic capacitance of each clock signal line is similar or even equal, avoiding different signal delays of adjacent clock signal lines, and avoiding signal delay changes caused by impedance changes of the clock signal lines, so that the display panel can display normally.