Clock Line Driver for Single-Cycle Pre-emption on Serial Bus
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Solution Overview
Problem
Conventional serial bus protocols, such as I2C and I3C, face challenges in efficiently handling urgent data transmission requests due to their half-duplex operation, leading to increased latency and reduced throughput, especially in complex applications where devices with high-priority data cannot quickly access the bus without completing ongoing transmissions.
Innovation Solution
The implementation of an in-band alert mechanism that allows pre-emption by transmitting additional pulses on the clock signal, enabling devices to request and initiate bus arbitration while data is being transmitted, thereby reducing latency and improving access to the serial bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional half-duplex serial bus protocols are used for data transmission, then device compatibility and protocol simplicity are maintained, but bus latency increases and throughput decreases when devices need to access the bus urgently
Solution Approach 1:
The patent implements preliminary action by allowing devices to assert pre-emption requests using pulse signals on the clock line before they need bus access. This enables the master device to detect upcoming high-priority requests in advance and prepare for bus ownership handoff, reducing the actual latency when urgent data transmission is needed while maintaining compatibility with conventional half-duplex protocols
2Device complexity
If conventional half-duplex serial bus protocols are used for data transmission, then protocol simplicity is maintained, but data communication throughput decreases when multiple devices compete for bus access
Solution Approach 1:
The patent applies periodic action by using regular clock signal cycles to carry both data transmission and pre-emption requests. Devices can assert pre-emption requests at specific periodic intervals (during clock cycles when SDA is stable), allowing multiple devices to compete for bus access efficiently without complicating the overall protocol structure, thereby improving throughput while maintaining protocol simplicity
3Stability of the object's composition
If the clock line driver remains active continuously, then clock signal stability is maintained, but the ability to detect pre-emption requests from other devices is blocked
Solution Approach 1:
The patent implements dynamics by making the clock line driver's impedance state changeable rather than fixed. The driver transitions between low-impedance (active driving) and high-impedance (releasing) states based on whether a pre-emption request is detected. This dynamic adjustment allows the system to maintain clock stability during normal operation while enabling detection of pre-emption requests when the driver releases the line
4Reliability
If bus arbitration is initiated only after current transmission completes, then data integrity is ensured, but access time for high-priority devices increases
Solution Approach 1:
The patent applies preliminary action by detecting pre-emption requests during ongoing data transmission and initiating arbitration procedures in advance. When a pre-emption pulse is detected on the clock line, the master device can start arbitration logic execution before the current transmission fully completes, reducing the access time for high-priority devices while maintaining data integrity through controlled handoff procedures
Data Source
AI summary
Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.