Clock Load Compensation for Deterministic Jitter Reduction
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Solution Overview
Problem
Conventional clock signal generation techniques face challenges in reducing deterministic jitter and circuit area while maintaining performance, as they often require increased bypass capacitance and power consumption to manage frequency-dependent supply loading variations.
Innovation Solution
A clock circuit with an auxiliary loading circuit that selectively provides load compensation on a regulated voltage node, adjusting the load current based on a vacillating divide value to minimize power supply variations and jitter, thereby reducing the need for excessive bypass capacitance and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bypass capacitance is increased to reduce deterministic jitter, then jitter performance is improved, but circuit area and power consumption increase
Solution Approach 1:
An auxiliary loading circuit is introduced as an intermediary component between the voltage regulator and the frequency divider. This auxiliary circuit actively compensates for load current variations by injecting compensating current, thereby reducing deterministic jitter without requiring increased bypass capacitance. The intermediary circuit mediates the interaction between the regulator and frequency divider, eliminating the need for excessive capacitance while maintaining jitter performance.
Solution Approach 2:
The invention changes the operating parameters of the voltage regulator by dynamically adjusting the load current through the auxiliary loading circuit. By varying the compensation current based on the divide value, the system optimizes the regulator's output impedance and load current characteristics, reducing deterministic jitter without increasing bypass capacitance. This parameter adjustment allows the system to achieve better jitter performance with reduced circuit area.
2Reliability
If bypass capacitance is increased to reduce deterministic jitter, then jitter performance is improved, but power consumption increases
Solution Approach 1:
The auxiliary loading circuit serves as an intermediary that actively manages load current variations, replacing the passive energy-dissipating approach of increased bypass capacitance. By introducing this active compensation mechanism, the system reduces deterministic jitter through controlled current injection rather than relying on large capacitance values that would increase power consumption.
Solution Approach 2:
The system dynamically changes the load current parameter through the auxiliary circuit based on the divide value, optimizing power efficiency. By adjusting the compensation current rather than maintaining fixed large bypass capacitance, the system achieves reduced deterministic jitter with lower overall power consumption.
3Reliability
If voltage regulator bandwidth is increased to reduce deterministic jitter, then jitter performance is improved, but circuit complexity and area increase
Solution Approach 1:
Instead of increasing the voltage regulator's bandwidth, the invention introduces an auxiliary loading circuit as an intermediary that handles load compensation externally. This approach achieves deterministic jitter reduction through load current management rather than through high-bandwidth voltage regulation, thereby avoiding the complexity and area penalties associated with increased regulator bandwidth.
4Reliability
If load compensation is applied to reduce deterministic jitter, then jitter performance is improved, but device complexity increases
Solution Approach 1:
The load compensation function is segmented into a separate auxiliary loading circuit that operates independently from the main voltage regulator. This segmentation allows the compensation function to be added without fundamentally redesigning the regulator architecture, thereby limiting the increase in overall device complexity while achieving improved deterministic jitter performance.
Data Source
AI summary
A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.