Clock Supply Circuit Power-Down During Locking in Semiconductor Memory
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Solution Overview
Problem
Semiconductor devices face limitations in entering power-down mode due to the need for clock supply circuit locking, leading to increased current consumption as internal circuits cannot enter power-down during locking periods.
Innovation Solution
A semiconductor device configuration that allows internal circuits to enter power-down mode independently of the clock supply circuit, with the clock supply circuit entering power-down only after locking is completed, using a controller to manage the power-down signal and locking signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor device enters power-down mode during clock supply circuit locking period, then current consumption is reduced, but the clock supply circuit cannot generate stable internal clock
Solution Approach 1:
The device is divided into two independent power-down control paths: one for internal circuits (which can enter power-down during locking) and one for the clock supply circuit (which must remain active during locking). This segmentation allows each part to operate independently according to its specific requirements, resolving the contradiction between current reduction and clock stability.
Solution Approach 2:
The controller monitors the locking status of the clock supply circuit and only permits the clock supply circuit to enter power-down mode after locking is confirmed. This preliminary check ensures that the internal clock is stable before allowing the clock supply circuit to power down, preventing clock instability while still enabling power savings.
2Reliability
If the clock supply circuit remains active during locking period, then stable clock generation is ensured, but current consumption increases
Solution Approach 1:
The power-down capability is segmented between internal circuits and the clock supply circuit. Internal circuits can enter power-down mode during the locking period to reduce current consumption, while the clock supply circuit remains active to ensure stable clock generation. This resolves the contradiction by allowing both requirements to coexist in different parts of the system.
Solution Approach 2:
The power-down mode entry is made dynamic and conditional rather than static. The controller dynamically adjusts which circuits can enter power-down based on the locking status, allowing maximum power savings while maintaining clock stability when required.
3Loss of energy
If internal circuits enter power-down mode during locking, then current consumption is reduced, but clock synchronization may be disrupted
Solution Approach 1:
The controller checks the locking status before allowing internal circuits to enter power-down mode. By performing this preliminary verification, the system ensures that clock synchronization will not be disrupted, as the clock supply circuit is already locked and stable. This resolves the contradiction by preventing power-down entry under unsafe conditions.
Solution Approach 2:
The system uses feedback from the locking status signal to control power-down mode entry. The controller continuously monitors whether the clock supply circuit is locked and uses this feedback information to make real-time decisions about power-down mode, ensuring that clock synchronization is maintained while maximizing power savings.
Data Source
AI summary
A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal.