Clock Management Circuit Frequency Transition Steps
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Solution Overview
Problem
Existing SoC designs face issues with sudden changes in system clock frequency, which can cause voltage droop or overvoltage, leading to indeterminate behavior and potential circuit damage due to sudden changes in current consumption.
Innovation Solution
A clock management circuit that gradually adjusts the system frequency by incrementing and decrementing the divisor value of a clock divider in controlled steps, allowing the clock signal to stabilize at the new frequency without sudden changes, thereby preventing voltage droop or overvoltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the system frequency is increased suddenly to improve performance, then the processing speed is improved, but the voltage regulator output voltage drops below the minimum safe operating level causing logic state corruption
Solution Approach 1:
The frequency transition is segmented into multiple intermediate steps rather than a single abrupt change. The clock management circuit divides the frequency transition into a sequence of smaller frequency increments, allowing the voltage regulator to adjust its output voltage progressively at each step, preventing voltage droop below the minimum safe operating level.
Solution Approach 2:
The clock management circuit performs preliminary actions by pre-calculating and preparing the sequence of intermediate frequency steps before executing the frequency transition. This allows the system to proactively manage the voltage regulator's response time and ensure voltage stability is maintained throughout the transition process.
2Adaptability or versatility
If the system frequency is adjusted abruptly to change performance levels, then the performance adaptability is improved, but the voltage level fluctuates causing indeterminate behavior and potential processing exceptions
Solution Approach 1:
The broad frequency adjustment range is segmented into multiple controlled intermediate frequency steps. Each step represents a manageable frequency increment that allows the voltage regulator to maintain stable output voltage, eliminating the harmful voltage fluctuations that would occur with abrupt frequency changes.
Solution Approach 2:
The frequency adjustment process is made dynamic and adaptive through the clock management circuit, which automatically selects and executes the appropriate sequence of intermediate frequency steps based on the desired target frequency. This dynamic approach maintains voltage stability while enabling flexible frequency adaptation.
3Loss of time
If the clock frequency is changed instantly to meet performance requirements, then the response time is improved, but the current consumption changes suddenly causing voltage droop in the regulator
Solution Approach 1:
The frequency transition is segmented into multiple rapid intermediate steps that collectively achieve the desired frequency change in minimal total time. While the transition occurs over multiple steps rather than instantly, each step is executed quickly, and the segmentation allows current consumption to increase gradually, preventing voltage droop.
Solution Approach 2:
The frequency adjustment is performed through periodic incremental changes rather than a single abrupt change. The clock management circuit applies periodic frequency increments at controlled intervals, allowing the voltage regulator to maintain stable output voltage while still achieving the frequency transition efficiently.
Data Source
AI summary
A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.