Clock Management System for Single Pin Serial Interface

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Solution Overview

Problem

Conventional systems face high power consumption due to always-active clocking functions in portable devices with serial interfaces, even when data transmission is idle, which contradicts the need for low power consumption and longer battery life.

Innovation Solution

A versatile clock management system that enables clocking functionality on a single-pin serial interface to be cycled on or off as needed, powering down when idle to reduce overall system power consumption, utilizing a self-enable/self-disable mechanism within the clocking system and embedding clock initiation and duration parameters within the serial data transmission frames.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If clocking functions are kept always active in serial interface systems, then data transmission reliability is maintained, but power consumption increases significantly

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The clocking system transitions from a static always-on state to a dynamic state that adapts to operational needs. The clock signal is enabled during active data transmission and disabled during idle periods, creating a dynamic power management regime that resolves the contradiction between reliability and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The clocking function operates periodically rather than continuously, being activated only when data transmission occurs and deactivated during idle intervals. This periodic operation pattern maintains data transmission reliability when needed while dramatically reducing average power consumption during idle periods.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If clocking is powered down during idle periods, then power consumption is reduced, but clock recovery from power-down states becomes necessary

Engineering Contradiction:
Improvepower consumptionVSAvoidclock recovery mechanism complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The system prepares for clock recovery in advance by embedding synchronization information within the serial data transmission frames. This preliminary embedding of timing information ensures that when the clock is re-enabled after power-down, the receiving end is already prepared to synchronize, reducing the complexity of the recovery mechanism.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The serial interface protocol itself carries the information necessary for clock recovery, making the system self-sufficient. The embedded synchronization data within the data frames enables automatic clock resynchronization without requiring external intervention or complex additional recovery circuitry.

Inventive Principle:
Principle #25Self-service

3Speed

If interface circuitry remains active for clocking, then data transmission speed is maintained, but unnecessary power is consumed during idle periods

Engineering Contradiction:
Improvedata transmission speedVSAvoidunnecessary power consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

Instead of maintaining full clocking operation continuously, the system applies partial action by enabling the clock only for the specific duration when data transmission is occurring. This partial operation eliminates excessive power consumption during idle periods while maintaining full transmission speed when data needs to be transmitted.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7716507B1Versatile clock management system for a single pin serial interface protocol
Publication Date: 2010.05.11 NAT SEMICON CORP
  • US7716507B1 patent drawing
  • US7716507B1 patent drawing
  • US7716507B1 patent drawing

AI summary

The present invention provides a versatile system for management of clocking for a serial interface. Serial input data, comprising a plurality of fields, and preceded by a specific input pattern, is provided to a receiver element. Within one of the fields in the serial input data, some information concerning the size the current serial data payload is included. Responsive to receiving the specific input pattern, the system of the present invention asserts a clock enable signal to activate clocking. A countdown corresponding to the size the current serial data payload is initiated. Once that countdown has reached zero, the clocking for the interface is disabled.