Clock Manipulation Module for Scan Chain Speed Path Testing
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Solution Overview
Problem
Modern integrated circuits face challenges in testing due to limited test points, making it difficult to identify issues that arise during high-speed operation, as existing scan testing methods are inefficient in locating "speed paths" where circuit elements fail at increased clock speeds.
Innovation Solution
The implementation of a clock manipulation module that adjusts clock signal edges in response to predetermined conditions, allowing for the identification of specific clock cycles where errors occur, enabling quicker debugging of speed paths through auto-step features that automatically increment clock cycles to pinpoint problematic cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan testing is performed at low clock speed, then the integrated circuit passes most tests, but speed paths cannot be identified
Solution Approach 1:
The patent dynamically adjusts the clock signal characteristics during testing. The clock manipulation module modifies clock edge timing based on detected error patterns, transitioning from static low-speed testing to dynamic variable-speed testing. This allows the system to automatically identify speed paths by observing where timing variations cause test failures, resolving the contradiction between maintaining high pass rates and identifying speed paths.
Solution Approach 2:
The system changes clock signal parameters (edge timing, frequency) during the testing process. By manipulating clock edges and varying the timing characteristics, the system can probe different speed paths without requiring separate high-speed test configurations. This parameter variation enables speed path identification while maintaining overall test reliability.
2Difficulty of detecting and measuring
If the clock speed is increased to identify speed paths, then speed paths can be detected, but the number of failing tests increases
Solution Approach 1:
Instead of applying high-speed stress to the entire circuit simultaneously, the patent applies clock manipulation selectively and partially. The clock manipulation module targets specific clock edges and cycles based on detected error patterns, applying timing variations only where needed to identify speed paths. This partial application maintains overall test pass rates while still enabling speed path detection.
Solution Approach 2:
The system uses feedback from test results to guide clock manipulation. When errors are detected, the clock manipulation module adjusts clock edge timing in subsequent test cycles based on this feedback. This closed-loop approach allows the system to identify speed paths progressively without causing widespread test failures, as the manipulation is refined based on actual circuit behavior.
3Measurement precision
If manual debugging of speed paths is performed, then accurate identification is possible, but debugging time is excessive
Solution Approach 1:
The patent implements self-service debugging through automated clock manipulation and error analysis. The system automatically detects errors, manipulates clock signals to isolate problematic paths, and identifies speed paths without requiring manual intervention. This self-service capability maintains high identification accuracy while dramatically reducing debugging time compared to manual methods.
Solution Approach 2:
The system performs preliminary clock manipulation and error analysis automatically during the testing phase itself. By preparing and analyzing test data with clock variations already applied, the system identifies speed paths before manual debugging would be required. This preliminary automated action eliminates the time-consuming manual debugging process while maintaining accurate identification.
Data Source
AI summary
A circuit including a clock module, a control module, a manipulation module, and a function module. The clock module generates a first clock signal. The control module generates a control signal. The manipulation module, based on the control signal, either (i) forwards the first clock signal without modifying the first clock signal or (ii) modifies a cycle of the first clock signal to simulate a second clock signal. The second clock signal has a frequency higher than a frequency of the first clock signal. The function module: during a first mode and based on a non-modified cycle of the first clock signal, operates devices in a predetermined configuration; ceases operating in the first mode and changes the predetermined configuration of the devices to form a scan chain; and during a second mode and based on the modified cycle, operates the scan chain to test the devices.