Clock Mesh Smart Decloning for Power Savings
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Solution Overview
Problem
Clock skew in digital circuit systems, where the clock signal arrives at different components at different times due to variations in wire length, temperature, and material imperfections, poses a challenge in maintaining proper timing and increasing clock frequency, leading to inefficiencies and potential failure to meet design goals.
Innovation Solution
A method and apparatus for de-cloning clock-gater cells in a digital circuit model by identifying clusters of clock-gater cells with common input signals, calculating clustered sub-portions, and reducing the number of clock-gater cells to a new clock-gater cell while replacing each with a matching buffer cell, thereby adjusting clock latency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve system performance, then productivity increases, but clock skew becomes more critical and timing accuracy deteriorates
Solution Approach 1:
The clock network is segmented into multiple zones based on spatial proximity and signal characteristics. Clock-gater cells are grouped into clusters that share common control signals, allowing independent optimization of each segment's timing without affecting the entire network. This segmentation enables higher overall clock frequencies by managing timing variations locally within each cluster.
Solution Approach 2:
The patent implements dynamic clock gating control where clock-gater cells can be selectively enabled or disabled based on operational requirements. By dynamically adjusting which clock-gater cells are active and grouping them into clusters, the system can optimize timing accuracy for critical paths while maintaining high clock frequencies for non-critical operations.
2Adaptability or versatility
If multiple clock-gater cells are used to control different logic circuits, then adaptability increases, but power consumption increases due to redundant cells
Solution Approach 1:
Clock-gater cells that share common control signals and serve similar functional purposes are merged into shared clusters. Instead of having separate clock-gater cells for each logic circuit, the patent groups them so that a single clock-gater cell can control multiple logic circuits within a cluster, significantly reducing the total number of clock-gater cells and their associated power consumption while maintaining the ability to independently control each circuit when needed.
Solution Approach 2:
The patent designs clock-gater cells with universal control capabilities that allow a single clock-gater cell to serve multiple logic circuits through shared control signals. This multi-functionality enables one clock-gater cell to replace what would traditionally require multiple separate cells, reducing power consumption while preserving adaptability through programmable or configurable control logic.
Data Source
AI summary
According to one general aspect, a method may include receiving a digital circuit model. The digital circuit model may include models of a clock mesh configured to provide a clock signal to a plurality of logic circuits, and a plurality of logic circuits, each logic circuit at least partially controlled by an application of the clock signal to one or more clock-gater cells. The method may include identifying a group of clock-gater cells having common input signals. The method may include calculating at least one clustered sub-portion of the group of clock-gater cells based upon a set of bounding dimensions, wherein each clustered sub-portion includes a plurality of clock-gater cells. The method may further include, for each clustered sub-portion, de-cloning in the digital circuit model the clock-gater cells by reducing the clock-gater cells to a new clock-gater cell and replacing the each clock-gater cell with a matching buffer cell.