Clock Mesh Gating with Activity-Driven Register Clustering
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Solution Overview
Problem
Existing clock mesh network designs for high-end microprocessors do not effectively utilize power-saving techniques like clock gating and register clustering, particularly due to the inapplicability of clock gating on stub wires connecting grid wires to sink registers, leading to significant power dissipation and skew variations.
Innovation Solution
The method involves connecting sink registers using steiner tree connections, clustering registers based on switching activity and timing slack, and inserting integrated clock gating cells to reduce power dissipation and clock skew, while preserving non-negative timing slack and optimizing register placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock mesh network uses redundant mesh grid wires near sink registers to achieve tolerance to variations, then clock skew variation is reduced, but power dissipation increases
Solution Approach 1:
The clock network is segmented into a global mesh grid and local trees connecting to sink registers. This segmentation allows the mesh to provide global tolerance while local trees reduce the redundant wiring needed near each sink, thereby reducing power dissipation while maintaining variation tolerance.
Solution Approach 2:
Different parts of the clock network are given different structures: the global mesh provides tolerance to variations, while local buffer-less trees connect to sinks with minimal redundancy. This local quality differentiation reduces overall power dissipation while preserving the tolerance benefit where it is most needed.
2Loss of energy
If clock gating is applied on stub wires to save power, then power dissipation is reduced, but clock gating becomes inapplicable due to buffer-less design
Solution Approach 1:
The local trees are designed to be dynamic in structure, allowing clock gating cells to be inserted at strategic points within the tree network. This dynamic design enables power savings through clock gating while maintaining the buffer-less architecture's efficiency, resolving the contradiction between power savings and structural constraints.
3Ease of manufacture
If registers are connected individually to mesh grid wires, then clock distribution is simple, but routing wirelength increases and power dissipation increases
Solution Approach 1:
Multiple sink registers are merged into local tree structures that connect to the mesh grid at shared points. This merging reduces the total routing wirelength compared to individual connections while maintaining simple clock distribution through the mesh grid, thereby resolving the contradiction between manufacturing simplicity and routing efficiency.
4Loss of energy
If integrated clock gating cells are inserted to reduce power dissipation, then power consumption is reduced, but chip area increases due to inserted cells
Solution Approach 1:
Clock gating cells are inserted partially - only at strategic points within the local trees where they provide maximum power savings with minimum area overhead. This partial application of clock gating achieves significant power reduction without the full area cost of gating every connection, resolving the contradiction between power savings and area consumption.
Data Source
AI summary
A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.