Clock Mesh Skew Controller Using Pulse-Width Delay Adjustment
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Solution Overview
Problem
Integrated circuits face challenges in minimizing clock skews between multiple clock meshes due to imbalances in clock distribution networks, which can lead to synchronization issues and increased power dissipation.
Innovation Solution
A clock skew controller is introduced, comprising a pulse generator, pulse width detector, and clock delay adjuster, which detects phase differences between clock meshes and adjusts clock delays to minimize skews by generating a digital signal corresponding to the pulse width and using it to delay one of the clocks, thereby synchronizing the clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mesh-type clock network is employed to reduce clock skew, then clock skew is reduced, but power dissipation increases
Solution Approach 1:
The clock network is divided into multiple separate clock meshes instead of using a single large mesh. Each mesh independently serves a portion of the circuit, reducing the total power consumption while maintaining low clock skew within each segment. The patent implements this by creating multiple clock meshes (first clock mesh, second clock mesh, etc.) that are distributed across the integrated circuit.
Solution Approach 2:
Different regions of the integrated circuit are assigned different clock meshes with optimized characteristics for their local requirements. Each clock mesh is designed to serve specific circuit components in its vicinity, allowing local optimization of power consumption and skew characteristics. The patent applies this by distributing multiple clock meshes across different regions of the circuit.
2Loss of energy
If multiple clock meshes are employed to reduce power dissipation, then power dissipation is reduced, but clock skew imbalance between meshes increases
Solution Approach 1:
A feedback mechanism is implemented to detect and correct clock skew imbalances between different clock meshes. The patent uses a skew detector that monitors the phase differences between clocks from different meshes and generates control signals to adjust delay elements, thereby dynamically balancing the clock skews across all meshes.
Solution Approach 2:
The patent dynamically adjusts the delay parameters of clock signals by introducing controllable delay elements whose delay values are modified based on detected skew conditions. This allows the system to change the timing parameters of clock distribution to achieve balance across multiple meshes, resolving the skew imbalance problem while maintaining low power consumption.
Data Source
AI summary
A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.