Clock Mesh Skew Scheduling for Digital Circuit Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock skew, a phenomenon where clock signals arrive at different times in synchronous digital circuits due to variations in wire length, temperature, and material imperfections, poses challenges in maintaining proper timing as clock rates increase, especially in high-frequency digital systems.
Innovation Solution
A method involving a clock mesh design that identifies clusters of end-points controlled by a common clock signal, determines timing slack, and adjusts clock-gater cells and skew-buffers to set a common latency, inserting skew-buffers based on individual end-point schedules to manage clock skew, thereby optimizing clock latency across the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock rate is increased to improve processing speed, then productivity increases, but clock skew becomes more critical and timing reliability deteriorates
Solution Approach 1:
The patent applies local quality by implementing individual skew schedules for different clusters of end-points within the clock network. Each cluster receives customized skew adjustment based on its specific timing requirements, rather than applying a uniform clock distribution. This allows the system to maintain high clock rates while compensating for local variations in path length and loading effects.
Solution Approach 2:
The patent changes the timing parameters of the clock signal by introducing variable skew schedules that adjust the clock arrival time at different end-points. By dynamically modifying the clock signal parameters (arrival time, phase) across different regions of the circuit, the system can operate at higher frequencies while maintaining timing integrity despite variations in wire length and loading.
2Measurement precision
If clock skew is minimized to improve timing precision, then measurement precision improves, but device complexity increases due to additional skew control circuits
Solution Approach 1:
The patent segments the clock network into multiple clusters of end-points, each with its own skew schedule. This segmentation allows timing precision to be optimized for each cluster independently while using standardized skew control circuits. The segmentation approach reduces overall complexity by breaking down the large-scale skew management problem into smaller, manageable sub-problems that can be handled by identical circuit blocks.
Solution Approach 2:
The patent implements universal skew control circuits that can be applied to multiple clusters throughout the clock network. These multi-functional circuits perform the same skew adjustment function across different regions, reducing the need for custom-designed control logic for each cluster. The universal approach maintains timing precision while minimizing device complexity through reuse of proven circuit designs.
3Measurement precision
If individual skew schedules are implemented for each end-point to improve timing accuracy, then timing precision improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments end-points into clusters that share common skew schedules, representing a compromise between individual customization and manufacturing simplicity. By grouping end-points with similar timing requirements into clusters, the system achieves adequate timing accuracy without requiring unique skew control circuits for every single end-point, thereby simplifying the manufacturing process.
Solution Approach 2:
The patent implements partial customization by applying skew schedules at the cluster level rather than the individual end-point level. This partial action approach provides sufficient timing accuracy for most applications while significantly reducing manufacturing complexity compared to fully individualized skew control. The clustering strategy represents a practical compromise that achieves the necessary timing precision without excessive manufacturing burden.
Data Source
AI summary
According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule.


