Clock Signal Mixing for Digital Circuit Test Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current structural testing methods for digital integrated circuits face inefficiencies and inaccuracies due to the need for separate test patterns and the negative effects of voltage droop during at-speed testing, which can distort results and reduce test precision.
Innovation Solution
A method that mixes high-speed and low-speed clock signals during structural testing, allowing for simultaneous stuck-bit and at-speed testing without initializing test control logic, and enabling arbitrary mixing of clock signals to reduce the number of tests and mitigate voltage droop effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If at-speed testing is performed with multiple clock pulses, then the circuit can be tested for manufacturing defects, but voltage droop occurs which distorts test results and reduces measurement precision
Solution Approach 1:
The patent implements periodic action by alternating between high-speed clock pulses (for at-speed testing) and low-speed clock pulses (for stuck-bit testing) in a periodic sequence. This periodic switching allows the circuit to undergo comprehensive testing while periodically recovering from voltage droop effects, thereby maintaining measurement precision throughout the testing process.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the clock pulse frequency parameter during testing. The testing device switches between high-frequency clock pulses (for at-speed testing) and low-frequency clock pulses (for stuck-bit testing), changing the operating parameters to mitigate voltage droop and maintain accurate measurements across different testing phases.
2Reliability
If separate test patterns are used for stuck-bit testing and at-speed testing, then comprehensive defect detection is achieved, but test time increases and productivity decreases
Solution Approach 1:
The patent merges stuck-bit testing and at-speed testing into a single integrated testing sequence. By combining both testing types in one test run with alternating clock pulse sequences, the patent eliminates the need for separate test patterns and reduces the total number of tests required, thereby improving productivity while maintaining comprehensive defect detection.
Solution Approach 2:
The patent implements universality by creating a single testing sequence that serves multiple functions: it performs both stuck-bit testing and at-speed testing using the same test pattern and clock infrastructure. This multi-functional approach eliminates redundant testing operations and streamlines the overall testing process.
3Measurement precision
If high-speed clock pulses are used for at-speed testing, then the circuit operates at expected frequency, but voltage droop increases which distorts later cycle results
Solution Approach 1:
The patent applies preliminary anti-action by inserting low-speed clock pulses between sequences of high-speed clock pulses. These low-speed pulses act as recovery intervals that allow voltage to stabilize before the next at-speed testing sequence, thereby counteracting the harmful voltage droop effect before it can distort test results.
Solution Approach 2:
The patent uses periodic action by implementing a repeating pattern of high-speed and low-speed clock pulses. This periodic structure ensures that voltage droop is periodically addressed through low-speed recovery cycles, maintaining measurement precision throughout extended at-speed testing sequences.
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.