Clock Mode Configuration Circuit for Chained Memory Interfaces
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Solution Overview
Problem
The existing parallel configuration of Flash memory systems faces performance limitations due to signal integrity issues like crosstalk, signal skew, and simultaneous switching noise, as well as increased power consumption and clock distribution challenges, which restrict the number of memory devices that can be connected effectively.
Innovation Solution
A serially connected memory system with a ring topology configuration, where memory devices are connected in series, allowing for the use of either parallel or source synchronous clock signals, and employing a configurable clock mode circuit to adapt to different signaling formats, thereby improving signal integrity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity is degraded by crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The system segments the memory devices into different connection groups: some devices are connected in parallel to the host controller while others are connected in series in a chain. This segmentation allows the parallel-connected devices to provide high storage capacity while the series-connected devices maintain signal integrity, as they are not subject to the same crosstalk and switching noise issues as parallel connections.
Solution Approach 2:
The host controller acts as an intermediary that manages both parallel and series connections. It receives data from parallel-connected devices and can also interface with series-connected devices, coordinating the operations between different connection types to maintain overall system reliability while achieving high storage capacity.
2Quantity of substance
If more memory devices are connected in parallel, then storage capacity increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
The system segments memory devices into parallel and series connection groups. Series-connected devices experience reduced power consumption because they share signal tracks and do not require independent frequent charging and discharging of long signal lines for each device, thus reducing overall power consumption while still providing increased storage capacity through the combination of multiple devices.
3Quantity of substance
If more memory devices are connected in parallel, then storage capacity increases, but clock distribution becomes more difficult and system performance is limited
Solution Approach 1:
The system segments clock distribution into two paths: a parallel clock signal path to parallel-connected devices and a series clock signal path to series-connected devices. This segmentation simplifies clock distribution by allowing the series-connected devices to share a single clock line, reducing the complexity of routing and synchronizing clocks to numerous parallel devices while still supporting large storage capacity.
4Quantity of substance
If parallel configuration is used to connect multiple memory devices, then storage capacity increases, but the number of devices is restricted due to drive capability limitations
Solution Approach 1:
The system segments the connection architecture into parallel and series portions. Series-connected devices can be chained together without being limited by the drive capability of a single host controller pin, as they share signal lines. This allows many more devices to be connected beyond what a purely parallel configuration would permit, while still achieving high storage capacity through the combined parallel and series arrangement.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.