Clock Mode Determination via Divide Ratio Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing audio devices require user intervention or additional pins to select the proper divisor for generating an internal master clock signal, limiting their ability to support a wide range of data sampling frequencies and divide ratios, and are prone to variations due to changes in fabrication process and temperature.
Innovation Solution
A system that measures the frequency of a received external master clock signal directly, eliminating the need for pre-divide operations, and uses a fixed frequency clock signal to determine the operating mode by measuring the master clock frequency and its ratio with the data clock frequency, thereby reducing on-chip circuitry complexity and supporting a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pre-divide operations are used to determine clock mode, then the device can support multiple clock modes, but the on-chip circuitry complexity increases and the device requires additional pins for mode indication
Solution Approach 1:
The patent extracts the frequency measurement function from the complex pre-divide operation chain and implements it directly on the external master clock signal. By measuring the external MCK frequency directly and comparing it with the data clock frequency, the system determines the operating mode without requiring complex pre-divide circuitry or additional mode indication pins, thus reducing on-chip complexity while maintaining multi-mode support
Solution Approach 2:
The system automatically determines the clock operating mode by self-measuring the external master clock frequency and comparing it with the data clock frequency. This self-service approach eliminates the need for user intervention or additional control pins to indicate the current speed mode, as the device autonomously selects the appropriate divide ratio based on its own measurements
2Manufacturing precision
If user intervention is required to select the proper divisor, then the device can accurately generate the internal master clock signal, but the ease of operation deteriorates
Solution Approach 1:
The device performs self-configuration by automatically measuring the external master clock frequency and the data clock frequency, then autonomously determining the correct operating mode and selecting the appropriate divide ratio. This eliminates the need for user intervention while ensuring accurate internal master clock signal generation, as the system independently identifies the correct configuration based on actual frequency measurements
3Device complexity
If a fixed divide ratio is used, then the device complexity is reduced, but the adaptability to different data sampling frequencies is limited
Solution Approach 1:
The patent implements dynamic divide ratio selection by measuring both the external master clock frequency and the data clock frequency, then automatically selecting the appropriate divide ratio based on the measured frequencies. This dynamic adaptation allows the system to support multiple data sampling frequencies (single speed up to 48 kHz, double speed 48-96 kHz, quad speed above 96 kHz) without requiring complex fixed divide ratio circuitry, achieving versatility through adaptive measurement and selection
Data Source
AI summary
A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.