Memory Clock Mode Configuration for Serial Ring Signal Integrity
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, as well as power consumption problems, especially when a large number of memory devices are connected in parallel, which restricts the system's ability to operate at high speeds and increases costs.
Innovation Solution
A semiconductor device with a configurable input circuit that can operate in modes for receiving coincident or non-coincident clock and data edges, allowing for the generation of shifted clock edges within a data valid window, and a memory system with a ring topology configuration where memory devices are serially connected, enabling the use of either parallel or serial clock signals based on a reference voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent divides the parallel memory device connection into multiple serially connected memory devices forming a ring topology. Instead of connecting all devices in parallel which causes signal integrity issues, the system segments the connection into a series arrangement where data and clock signals are passed sequentially from one device to the next, eliminating crosstalk and simultaneous switching noise while maintaining high storage capacity through the combination of multiple devices.
2Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
The patent segments the parallel connection into a serial ring topology where each memory device processes and passes signals sequentially. This eliminates the need for frequent charging and discharging of multiple parallel signal tracks, significantly reducing power consumption while maintaining the ability to provide high storage capacity through the combination of multiple serially connected devices.
3Quantity of substance
If a large number of memory devices are connected in parallel to meet ultra-high capacity demands, then the storage capacity increases, but system complexity increases due to extensive clock distribution requirements
Solution Approach 1:
The patent segments the clock distribution system into individual serial connections between memory devices in a ring topology. Instead of distributing clock signals to all devices simultaneously through extensive parallel routing, each device receives and processes clock signals sequentially from its predecessor in the ring, dramatically reducing clock distribution complexity while supporting ultra-high storage capacity through the serial arrangement of multiple devices.
4Quantity of substance
If memory devices are connected in parallel to increase storage capacity, then the storage capacity increases, but operating speed decreases due to signal integrity issues
Solution Approach 1:
The patent segments the parallel connection into a serial ring topology that enables high-speed operation by eliminating signal integrity issues. The serial arrangement allows for cleaner signal transmission without crosstalk or skew, and the system achieves high operating speeds through the sequential processing and passing of data between devices in the ring, while maintaining high storage capacity through the combination of multiple devices.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.