Clock Frequency Modulation With Bounded Jitter Compensation
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Solution Overview
Problem
Frequency modulation of clock signals in automotive systems increases jitter beyond acceptable limits, preventing their use in communication interfaces due to excessive power consumption and area demands in prior art solutions that rely on additional clock sources.
Innovation Solution
A method that reduces jitter by subtracting a defined and predictable clock period error signal from the nominal clock period, limiting accumulated jitter to non-positive values, allowing frequency modulation without additional clock sources, and compensating by dropping clock pulses when the jitter limit is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If frequency modulation is applied to improve EMC characteristics, then electromagnetic compatibility is improved, but jitter increases beyond acceptable limits
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing compensation values in a lookup table before the modulation process. The compensation value is determined based on the modulation depth and frequency, allowing the system to pre-compensate for expected jitter without real-time complex calculations, thus maintaining both EMC improvement and jitter control
Solution Approach 2:
The patent implements feedback by continuously monitoring the actual jitter and comparing it against the acceptable budget. The compensation mechanism adjusts the clock signal phase or frequency based on the measured deviation, creating a closed-loop system that maintains jitter within acceptable limits while preserving EMC benefits
2Manufacturing precision
If a second independent clock signal is used to reduce jitter, then jitter reduction is achieved, but power consumption and area increase
Solution Approach 1:
The patent merges the jitter reduction function with the existing frequency modulation circuitry by integrating a compensation mechanism within the same clock generation block. This eliminates the need for a separate second clock source and its associated PLL circuitry, thereby reducing both power consumption and silicon area while maintaining jitter reduction capability
Solution Approach 2:
The patent applies self-service by enabling the clock signal generation circuit to compensate for its own jitter without requiring external assistance from a second independent clock source. The circuit uses its own resources (lookup tables, phase adjusters) to correct its performance, eliminating the need for additional power-hungry external clock generators
3Manufacturing precision
If a second independent clock signal is used to reduce jitter, then jitter reduction is achieved, but device complexity increases
Solution Approach 1:
The patent merges the jitter reduction function with the existing frequency modulation circuitry by integrating a compensation mechanism within the same clock generation block. This eliminates the need for a separate second clock source and its associated PLL circuitry, thereby reducing both power consumption and silicon area while maintaining jitter reduction capability
Data Source
AI summary
Embodiments relate to systems and methods for reducing jitter caused by frequency modulation of a clock signal including modulating the frequency of the clock signal based on a predetermined modulation signal m(t), and compensating an accumulated jitter J(t) caused by the frequency modulation of the clock signal such that an absolute value of the accumulated jitter J(t) never exceeds a predetermined jitter limit Jlim.