Clock-Monitored Reset Circuit for Safe RAM Initialization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic circuits face challenges in providing a reliable reset signal, especially in safety-critical systems where the system clock may not be running, leading to issues with asynchronous resets and potential data loss or corruption in RAM devices.
Innovation Solution
An electronic circuit with both synchronous and asynchronous reset signal paths, utilizing a clock monitoring unit to detect clock availability and route the reset signal accordingly, ensuring robust asynchronous resets without jeopardizing setup and hold times of synchronous blocks like RAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an asynchronous reset signal is used to reset the system when the clock is not running, then the system can be reset independently of clock state, but RAM devices may lose or corrupt data due to lack of synchronized reset
Solution Approach 1:
The reset signal path is segmented into two separate paths: a synchronous reset path that passes through synchronization logic for clocked devices like RAM, and an asynchronous reset path that bypasses synchronization for immediate reset capability. This segmentation allows each path to be optimized for its specific function while working together to resolve the contradiction between reset adaptability and data integrity.
Solution Approach 2:
A selection circuit acts as an intermediary that chooses between the synchronous and asynchronous reset paths based on system conditions. When the clock is running, the synchronous path is selected to maintain data integrity in RAM devices. When the clock is stopped, the asynchronous path is selected to enable reset capability. This intermediary mechanism resolves the contradiction by dynamically switching between the two reset modes.
2Adaptability or versatility
If separate signals for asynchronous and synchronous reset are generated with different routing, then reset can be applied to different device types, but device complexity and wiring increase
Solution Approach 1:
The patent merges the synchronous and asynchronous reset paths into a single integrated circuit block with a unified output. The selection circuit internally routes the appropriate reset signal based on clock availability, eliminating the need for separate external wiring for synchronous and asynchronous resets. This merging reduces wiring complexity while maintaining the adaptability to provide the appropriate reset type.
Solution Approach 2:
The reset circuit is designed as a universal module that can provide both synchronous and asynchronous reset functionality through a single interface. The selection circuit enables the same physical output to serve dual purposes: synchronized reset for clocked devices when the clock is running, and asynchronous reset for immediate reset when the clock is stopped. This multi-functionality reduces the need for separate routing while maintaining versatility.
3Reliability
If reset de-assertion is synchronized with the clock signal, then synchronous blocks can properly initialize, but the reset cannot be effectively applied when the clock is not running
Solution Approach 1:
The reset circuit dynamically adapts its behavior based on clock availability. When the clock is running, the circuit operates in synchronous mode where reset de-assertion is synchronized with the clock signal, ensuring proper initialization of synchronous blocks. When the clock is stopped, the circuit automatically switches to asynchronous mode, allowing reset to be applied independently of clock timing. This dynamic adaptation resolves the contradiction between reliable synchronous initialization and versatile reset applicability.
Data Source
AI summary
An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.