Glitch-Free Clock Multiplexer with Active Source Monitoring

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Solution Overview

Problem

Conventional clock multiplexing systems require both clocks to be active before and during the switching process, leading to potential glitches when switching between asynchronous or non-synchronous clock frequencies, which can disrupt system operations.

Innovation Solution

The system automatically switches to an active clock when one of the clocks is disabled, ensuring glitch-free operation by monitoring clock status and using delay circuit elements for proper timing, eliminating the need for a third clock to check the status of the two clocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional clock multiplexing is used to switch between different clock frequencies, then clock switching capability is improved, but glitches occur during switching between asynchronous or non-synchronous clock frequencies

Engineering Contradiction:
Improveclock switching capabilityVSAvoidglitch-free operation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting the disabled state of a clock source before switching occurs. The system monitors clock status in advance and prepares for switching by detecting when one clock becomes disabled, ensuring a smooth transition to the other clock source without glitches. This is achieved through status detection circuits that monitor clock signals and trigger switching operations proactively rather than reactively.

Inventive Principle:
Principle #10Preliminary action

2Difficulty of detecting and measuring

If a third clock is added to check the status of two clocks, then clock status monitoring is improved, but device complexity increases

Engineering Contradiction:
Improveclock status monitoringVSAvoidnumber of clock sources
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent applies universality by making each clock source monitor the status of the other clock source. Instead of requiring a dedicated third monitoring clock, the system enables the existing clock sources to perform dual functions: generating clock signals and monitoring each other's status. This is achieved through cross-coupled status detection circuits that allow each clock to detect when the other becomes disabled, eliminating the need for additional monitoring hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If both clocks must be active before and during switching, then switching control is simplified, but productivity is reduced due to inability to switch when one clock is disabled

Engineering Contradiction:
Improveswitching controlVSAvoidclock switching flexibility
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies dynamics by enabling the clock multiplexing system to adapt its behavior based on the real-time status of clock sources. The system dynamically adjusts the switching operation depending on whether one or both clocks are active. When one clock is disabled, the system automatically modifies the switching sequence to accommodate this condition, allowing seamless transitions even when clock sources are not symmetrically active. This dynamic adaptation maintains operational flexibility while ensuring reliable switching.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10198026B1Glitch-free clock multiplexer
Publication Date: 2019.02.05 AMAZON TECH INC
  • US10198026B1 patent drawing
  • US10198026B1 patent drawing
  • US10198026B1 patent drawing

AI summary

In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.