Clock Multiplexer for Asynchronous Domain Data Access
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Solution Overview
Problem
In control systems with split domains for power saving, accessing data between domains with asynchronous clocks results in synchronization issues, leading to increased reaction time and power consumption due to the need for synchronizer cells and waiting for clock edges, which limits access rate and increases power usage.
Innovation Solution
Synchronizing the clock of the slower domain with the faster domain's clock, eliminating the need for synchronizer cells by ensuring no collisions occur by accessing data only when the slower domain is not clocked, and using a clock multiplexer to select between asynchronous and synchronous clock modes based on the operation mode of the faster domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronizer cells are used to access data between domains with asynchronous clocks, then data access reliability is improved, but chip area increases and power consumption increases
Solution Approach 1:
The patent introduces a clock multiplexer as an intermediary component that selects between the first clock signal and the second clock signal based on operational mode. This mediator enables the system to switch between synchronous and asynchronous clock domains dynamically, eliminating the need for bulky synchronizer cells while maintaining data access reliability through controlled clock selection.
Solution Approach 2:
The system dynamically switches between different clock domains using a clock multiplexer controlled by a mode signal. When in first mode, the second domain operates with the first clock signal for synchronous access; when in second mode, it switches to the second clock signal for asynchronous operation. This dynamic adaptation eliminates static synchronizer cells and reduces chip area while maintaining reliability.
2Reliability
If synchronizer cells are used to access data between domains with asynchronous clocks, then data access reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between synchronous and asynchronous clock domains based on operational mode, eliminating the need for continuously active synchronizer cells. The clock multiplexer selectively enables the appropriate clock signal for the second domain, reducing power consumption by avoiding the continuous operation of synchronization hardware while maintaining data access reliability through controlled clock selection.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically by selecting between two different clock signals based on operational mode. This parameter change allows the system to operate in synchronous mode when reliability is critical or in asynchronous mode when power saving is prioritized, eliminating the need for power-hungry synchronizer cells while maintaining access reliability through mode-appropriate clock selection.
3Reliability
If waiting for clock edges is required for data access, then data access correctness is improved, but access rate decreases
Solution Approach 1:
The system dynamically switches between synchronous and asynchronous clock domains based on operational requirements. When high access rate is needed, the system operates in asynchronous mode with the second clock signal, eliminating the need to wait for slower clock edges. When data access correctness is critical, it switches to synchronous mode with the first clock signal. This dynamic switching maintains correctness while maximizing access rate through mode-appropriate clock selection.
Solution Approach 2:
The patent changes the clock frequency parameter by selecting between a slower first clock signal and a faster second clock signal based on operational mode. This parameter change allows the system to achieve higher access rates when operating in asynchronous mode with the faster clock, while maintaining data access correctness through controlled mode switching and appropriate clock selection for different operational requirements.
4Speed
If the second domain operates at high clock frequency for normal mode, then processing speed is improved, but power consumption increases when accessing slower domain data
Solution Approach 1:
The system dynamically switches the clock signal supplied to the second domain based on operational mode. In normal mode, the second domain operates at high frequency with the second clock signal for fast processing. When accessing data from the first domain, it switches to the first clock signal to match the slower domain's frequency, eliminating the need for frequency multiplication and reducing power consumption while maintaining processing capability.
Solution Approach 2:
The patent changes the operating frequency parameter of the second domain by selecting between two clock signals. When high processing speed is needed, it operates at the higher frequency of the second clock. When accessing data from the first domain, it switches to the lower frequency of the first clock, reducing power consumption by avoiding high-frequency operation during data access operations while maintaining the ability to switch back to high speed when needed.
Data Source
AI summary
An example relates to a method for accessing data of a first domain that is driven by a first clock via a second clock, comprising at least one of the following: accessing the data of the first domain via the second clock during a time when the first clock is in a first logical state. An edge indicating a transition from a second logical state to the first logical is used to access data via the first clock, or accessing the data of the first domain via the second clock at edges of the first clock that are synchronized with edges of the second clock.